🤖 AI Summary
Traditional HDLs operate at a low abstraction level, requiring manual control/scheduling, while existing functional hardware description tools lack automated scheduling and modular reuse. Method: This paper proposes a functional-programming-based high-level synthesis (HLS) framework that integrates Synchronous Dataflow–Actor Programming (SDF-AP) graph modeling with Haskell extensions—Template Haskell, QuasiQuotes, Generalized Algebraic Data Types (GADTs), and type-level programming—to enable end-to-end, automatic generation of hardware circuits from hierarchical functional specifications, including automatic derivation of data and control flows. Contributions/Results: We introduce (i) the first hierarchical pattern specification mechanism; (ii) GADT-based automatic construction of parameterized buffers; and (iii) built-in executable golden models for closed-loop verification. Experiments show that, compared to Vitis HLS, our framework significantly improves transparency in resource scheduling, timing predictability, and expressiveness of parallel architectures, while yielding more interpretable hardware designs and higher verification efficiency.
📝 Abstract
FPGAs provide highly parallel and customizable hardware solutions but are traditionally programmed using low-level Hardware Description Languages (HDLs) like VHDL and Verilog. These languages have a low level of abstraction and require engineers to manage control and scheduling manually. High-Level Synthesis (HLS) tools attempt to lift this level of abstraction by translating C/C++ code into hardware descriptions, but their reliance on imperative paradigms leads to challenges in deriving parallelism due to pointer aliasing and sequential execution models. Functional programming, with its inherent purity, immutability, and parallelism, presents a more natural abstraction for FPGA design. Existing functional hardware description tools such as Clash enable high-level circuit descriptions but lack automated scheduling and control mechanisms. Prior work by Folmer introduced a framework integrating SDF-AP graphs into Haskell for automatic hardware generation, but it lacked hierarchy and reusability. This paper extends that framework by introducing hierarchical pattern specification, enabling structured composition and scalable parallelism. Key contributions include: (1) automatic hardware generation, where both data and control paths are derived from functional specifications with hierarchical patterns, (2) parameterized buffers using GADTs, eliminating the need for manual buffer definitions and facilitating component reuse, and (3) provision of a reference"golden model"that can be simulated in the integrated environment for validation. The core focus of this paper is on methodology. But we also evaluate our approach against Vitis HLS, comparing both notation and resulting hardware architectures. Experimental results demonstrate that our method provides greater transparency in resource utilization and scheduling, often outperforming Vitis in both scheduling and predictability.