Implementing Homomorphic Encryption-Based Logic Locking in System-on-Chip Designs

2026-07-30

AI Summary

This work addresses the risk of sensitive information leakage in traditional logic locking, which requires exposing original parameters. For the first time, homomorphic encryption is integrated into logic locking by implementing a secure scheme based on Ring Learning with Errors (Ring-LWE) over binary rings within a RISC-V system-on-chip, safeguarding critical logic paths during privilege transitions. The proposed method enables unlocking without revealing the original key, substantially enhancing hardware intellectual property security. FPGA implementation results demonstrate that the locking module occupies only 3,519 LUTs and 2,645 registers, incurring modest overheads of 6.0% in LUTs and 6.9% in registers, with an unlocking latency of approximately 2.6 microseconds—imposing negligible impact on user-level performance.

Abstract

This study presents a logic locking scheme based on the binary Ring Learning With Errors algorithm, implemented in a RISC-V System-on-Chip design. Unlike traditional logic locking methods that require providing users with raw locking parameters, the proposed approach secures critical logic paths in the privilege switching process without exposing these sensitive parameters. The implemented locking module itself consumes 3519 Look-Up Tables and 2645 Registers, leading to an overall overhead of 6.0% in Look-Up Tables and 6.9% in Registers compared to the baseline system. The unlock process requires about 2.6 us, introducing moderate performance impact, primarily affecting system-level operations while preserving user-level computational efficiency.

Problem

• Homomorphic Encryption
• Logic Locking
• System-on-Chip
• Hardware Security
• Privilege Switching

Innovation

• Homomorphic Encryption
• Logic Locking
• Ring Learning With Errors
• RISC-V SoC
• Hardware Security