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Dynamic Tsetlin Machine Accelerators for On-Chip Training at the Edge using FPGAs
🤖 AI Summary
To address the demand for low-power, privacy-preserving, and real-time training on IoT edge nodes, this paper proposes an FPGA-based on-chip training accelerator built upon Dynamic Tsetlin Machines (DTMs), eliminating backpropagation and floating-point arithmetic in favor of interpretable binary logic rules—replacing conventional DNN training. We introduce a novel dynamically reconfigurable DTM architecture that supports runtime adaptation across datasets and model scales without requiring logic re-synthesis. Through efficient LUT mapping, BRAM optimization, and state-machine-driven learning, we achieve hardware-software co-optimization for both Vanilla and Coalesced TM algorithms. Experimental results demonstrate that our design achieves 2.54× higher energy efficiency (GOP/s/W) compared to the best prior work, reduces power consumption by 6×, and significantly improves training speed, energy efficiency, and deployment flexibility.
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📝 Abstract
The increased demand for data privacy and security in machine learning (ML) applications has put impetus on effective edge training on Internet-of-Things (IoT) nodes. Edge training aims to leverage speed, energy efficiency and adaptability within the resource constraints of the nodes. Deploying and training Deep Neural Networks (DNNs)-based models at the edge, although accurate, posit significant challenges from the back-propagation algorithm's complexity, bit precision trade-offs, and heterogeneity of DNN layers. This paper presents a Dynamic Tsetlin Machine (DTM) training accelerator as an alternative to DNN implementations. DTM utilizes logic-based on-chip inference with finite-state automata-driven learning within the same Field Programmable Gate Array (FPGA) package. Underpinned on the Vanilla and Coalesced Tsetlin Machine algorithms, the dynamic aspect of the accelerator design allows for a run-time reconfiguration targeting different datasets, model architectures, and model sizes without resynthesis. This makes the DTM suitable for targeting multivariate sensor-based edge tasks. Compared to DNNs, DTM trains with fewer multiply-accumulates, devoid of derivative computation. It is a data-centric ML algorithm that learns by aligning Tsetlin automata with input data to form logical propositions enabling efficient Look-up-Table (LUT) mapping and frugal Block RAM usage in FPGA training implementations. The proposed accelerator offers 2.54x more Giga operations per second per Watt (GOP/s per W) and uses 6x less power than the next-best comparable design.
Problem
Research questions and friction points this paper is trying to address.
Edge training challenges in IoT due to DNN complexity
Need for efficient FPGA-based on-chip ML training
Dynamic Tsetlin Machine as DNN alternative for edge
Innovation
Methods, ideas, or system contributions that make the work stand out.
FPGA-based Dynamic Tsetlin Machine accelerator
Logic-based on-chip inference with automata
Run-time reconfigurable for diverse datasets
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