A Progressive Approach to Synthesizable RTL Design Generation Using LLMs

2026-07-20

AI Summary

This work addresses the challenge that large language models (LLMs) often generate erroneous RTL code due to ambiguous or misinterpreted specifications, with such errors typically surfacing only during simulation and proving difficult to trace. To mitigate this, the paper proposes VeriRefine, a novel approach that first refines informal specifications into explicit Abstract Signal Transition Functions (ASTFs)—serving as a verifiable prelude to RTL generation. The method incorporates a five-layer auditing mechanism to validate design intent across dimensions including completeness, consistency, and FSM integrity, and enables targeted debugging by tracing simulation failures back to either specification misunderstandings or coding errors. Evaluated on RTLLM v2.0 and VerilogEval-Human v2, VeriRefine achieves functional correctness rates of 94.0% and 98.1%, respectively, substantially enhancing the reliability and synthesizability of LLM-generated RTL.

Abstract

Large language models can generate register-transfer-level (RTL) designs directly from natural language specifications. Their failures, however, arise mostly from understanding rather than coding \cite{zhang2026understanding, qiu2025towards}. A specification is informal and ambiguous, the model's interpretation stays implicit, and every misreading is committed silently into Verilog, where only simulation can expose it. Intermediate representations make the interpretation partly explicit, yet existing works don't verify the interpretation against the specification, and repair simulation failures at the code level regardless of where the misreading originated. VeriRefine instead treats specification refinement as a verifiable stage of RTL generation. It progressively refines the prose specification into an explicit, schema-constrained account of design intent, expressed as per-signal Abstract Signal Transition Functions (ASTFs) that commit each signal's logic style, clock domain, and reset behavior before any code exists and ground every behavior in a verbatim specification sentence. The refined specification then passes a five-layer audit spanning soundness, completeness, consistency, FSM integrity, and core RTL design rules, so interpretation errors are repaired at the representation level before any Verilog is generated. Once code is generated, each simulation failure is classified as an understanding error or a coding error and routed back to the corresponding stage for targeted repair. Because every signal's hardware class is fixed during refinement, synthesizability becomes a structural property of the pipeline rather than a post-hoc check. With Claude Sonnet 4.6, VeriRefine reaches 94.0\% functional correctness on RTLLM v2.0 and 98.1\% on VerilogEval-Human v2.

Problem

• RTL generation
• specification ambiguity
• interpretation error
• functional correctness
• synthesizability

Innovation

• specification refinement
• Abstract Signal Transition Functions
• verifiable RTL generation
• LLM-based hardware synthesis
• synthesizability by construction