PIP-NTT: Towards a Scalable Memory-Parallelized Accelerator for Iterative NTT in PQC

2026-07-20

AI Summary

Existing iterative NTT accelerators struggle to balance efficiency and scalability due to reliance on ping-pong memory architectures and large cyclotomic ring storage. This work proposes a parallelization strategy employing four small n/4-sized memory blocks, integrated with a multiplication-free rescaling architecture and a unified Cooley-Tukey/Gentleman-Sande butterfly unit, to realize a high-throughput, low-area pipelined NTT accelerator. The design supports mixed-radix butterfly computations and multiple post-quantum cryptographic schemes. Implemented on FPGA, it achieves area-time product improvements of 2.67× and 1.48× over the state-of-the-art area-optimized and throughput-optimized accelerators, respectively, significantly enhancing energy efficiency and scalability.

Abstract

The iterative forward and inverse number theoretic transform (NTT) is a key component in lattice-based post-quantum cryptography (PQC), typically implemented using Cooley-Tukey and Gentleman-Sande butterfly units. Existing iterative NTT accelerators often rely on ping-pong memory schemes and large memory blocks tied to the cyclotomic ring, which limits overall efficiency. To overcome this, we propose a memory-parallelization strategy using four smaller n/4-sized memories for ring size n, preserving the total memory footprint of conventional designs. We also introduce a multiplication-free rescaling architecture for the inverse NTT. Building on these innovations, we perform a comprehensive hardware-based design space exploration of unified Cooley-Tukey and Gentleman-Sande butterfly units, evaluating both coarse- and fine-grained pipelining strategies. The resulting optimized butterfly unit forms the core of our proposed pipelined and memory-parallelized NTT accelerator, "PIP-NTT". It integrates two such units alongside the memory-parallelization scheme to boost computational throughput under tight area constraints. Experimental results on FPGA platforms show that PIP-NTT achieves 2.67x and 1.48x higher efficiency in average Area-Time Product compared to the most area-optimized and high-speed NTT accelerators in the literature. The design is scalable across butterfly radices and adaptable to other PQC schemes, making it a versatile solution for future cryptographic hardware

Problem

• Number Theoretic Transform
• Post-Quantum Cryptography
• Memory Efficiency
• Iterative NTT
• Hardware Acceleration

Innovation

• memory-parallelization
• multiplication-free rescaling
• unified butterfly architecture
• pipelined NTT accelerator
• scalable PQC hardware