Mapping Without Graphs: Learning Coherence Traffic for Task Placement

๐Ÿ“… 2026-07-21
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๐Ÿค– AI Summary
Existing task mapping approaches struggle to effectively optimize multicore Network-on-Chip (NoC) performance due to their reliance on incomplete task graphs and neglect of cache coherence traffic. This work proposes CoTM, a novel framework that explicitly models cache coherence communication by dynamically inferring coherence behavior to construct a coherence-aware task graph. Building upon this representation, CoTM employs a lightweight heuristic algorithm combined with a multi-start optimization strategy to iteratively refine task placement. By moving beyond the limitations of conventional methods that depend solely on static or runtime program structure, CoTM significantly enhances mapping qualityโ€”achieving up to a 47.85% reduction in average link utilization and up to a 10.30% decrease in total energy consumption compared to state-of-the-art solutions.
๐Ÿ“ Abstract
Cache coherence is essential for communication in many-core Network-on-Chip (NoC)-based systems. As application scale and complexity increase, efficiently managing communication becomes increasingly challenging, making task mapping a key optimization technique. However, existing task mapping approaches suffer from two major limitations. First, they rely on predefined task graphs whose dependencies are typically derived from program structure or runtime information, such as dataflow, synchronization, traces, or profiling, without explicitly capturing coherence-induced interactions arising from shared data accesses. Consequently, these graphs provide only a partial representation of inter-task relationships, limiting mapping effectiveness. Second, they generally overlook cache coherence, even though coherence traffic constitutes a significant portion of NoC communication. This mismatch between modeled communication behavior and actual runtime interactions often leads to suboptimal mappings and degraded system performance. To address these limitations, we propose CoTM, a coherence-aware task mapping framework that constructs task graphs by inferring inter-task dependencies from dynamic coherence behavior. CoTM employs a lightweight heuristic with a multi-start optimization strategy to iteratively refine task placement, guided by a coherence-aware penalty function that jointly considers coherence traffic and NoC performance metrics. Experimental results demonstrate that CoTM reduces average link utilization by up to 47.85% and total energy consumption by up to 10.30% compared with existing approaches. These results highlight the importance of incorporating cache coherence into task mapping and demonstrate the potential of coherence-aware optimization for future many-core NoC systems.
Problem

Research questions and friction points this paper is trying to address.

task mapping
cache coherence
Network-on-Chip
coherence traffic
many-core systems
Innovation

Methods, ideas, or system contributions that make the work stand out.

coherence-aware mapping
task placement
Network-on-Chip
cache coherence
many-core systems
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