A Journey in Shared Memory Land

2026-08-01

AI Summary

This work addresses the high complexity of parallel programming and the conceptual divide between shared-memory and message-passing models by proposing a hybrid parallel model that integrates the strengths of both paradigms. Grounded in PRAM theory and enriched with asynchronous logic design principles, the approach co-optimizes hardware architecture and programming abstractions. Through a series of efforts—including MP-C, PLURAL, and Async Plural—the authors developed simplified parallel systems such as HAL and RC64, which substantially reduce programming complexity while maintaining high execution efficiency. These contributions significantly enhance the programmability of parallel applications and offer both theoretical foundations and practical paradigms for future parallel architecture design.

Abstract

I have greatly enjoyed spending many years in studying parallel computing. My journey goes thorough MP-C, PLURAL, Async Plural, HAL, RC64 and more. As a PhD student at Princeton I studied a combination of shared memory and message passing, motivated by algorithms and the ease of programming. While at the Technion, a brilliant MSc student figured out a better way for shared memory machines that further simplified parallel programming. He later founded Plurality and we developed the HAL machine. At Ramon Chips we reinvented RC64 and managed to make programming much easier. Theoretical computing models, especially PRAM, have constituted the foundation for my work. Fortunately, I spent many years learning the theory and practice of asynchronous logic, and applied some of these concepts towards improving, namely simplifying, parallel machines. Over the years I became disillusioned of inventive hardware designers and their innovative machines. That perspective helped crystalize this process. Still, much more remains to be done.

Problem

• parallel programming
• shared memory
• ease of programming
• parallel computing
• asynchronous logic

Innovation

• shared memory
• parallel programming
• asynchronous logic
• PRAM
• HAL architecture