A Time-Multiplexed Spiking Neural Network Accelerator with Pipelined Readout for FPGA Inference

2026-08-01

AI Summary

This work addresses the challenges of routing complexity and timing bottlenecks in deploying spiking neural networks (SNNs) on low-cost FPGAs. Focusing on the MNIST classification task, the authors design and implement a purely inference-oriented SNN hardware accelerator that integrates several key innovations: a time-multiplexed 1-bit spike input mechanism, distributed on-chip weight storage, an integer-based leaky integrate-and-fire (LIF) neuron model, and a pipelined readout architecture. To alleviate critical-path pressure, the design incorporates a multi-cycle pipelined argmax unit with a tie-breaking module. Implemented on an AMD Artix-7 FPGA, the accelerator achieves a clock frequency of 167 MHz, processes each image in 82 μs, consumes only 0.336 W of power, and attains an energy efficiency of 36,300 images per joule.

Abstract

Spiking Neural Networks (SNNs) provide a power-efficient neuromorphic alternative to traditional artificial neural networks by processing information through discrete temporal events. This paper presents the design and Field-Programmable Gate Array (FPGA) implementation of an inference-only SNN accelerator optimized for MNIST digit classification. To address the physical routing constraints and timing bottlenecks inherent in low-cost devices, we propose an optimized hardware microarchitecture featuring a time-multiplexed 1-bit spike-feeding mechanism governed by a finite state machine (FSM), localized distributed memory for weight storage, and an integer-based Leaky Integrate-and-Fire (LIF) neuron model with register widths selected to prevent overflow. In addition, a multi-cycle pipelined argmax and tie-breaker readout module eliminates the dominant combinational critical path. Implemented on an entry-level AMD Artix-7 FPGA (XC7A200T) using a 784-64-10 network topology, the proposed pipelined architecture increases the maximum operating frequency (Fmax) from 13.3 MHz to 167 MHz. Hardware evaluation demonstrates a sequential processing latency of 82 μs per image, enabling a 1,000-sample VHDL simulation batch to be completed in 0.082 s. Vivado post-implementation vector-based power analysis estimates the total on-chip power consumption at 0.336 W and the energy efficiency at approximately 36,300 samples per joule. These results demonstrate that the proposed microarchitecture provides a resource-efficient solution for real-time neuromorphic edge inference, provided that the network size remains within the practical limits of time-multiplexed execution.

Problem

• Spiking Neural Networks
• FPGA inference
• timing bottlenecks
• physical routing constraints
• neuromorphic edge inference

Innovation

• Time-Multiplexed Spiking Neural Network
• Pipelined Readout
• FPGA Accelerator
• Leaky Integrate-and-Fire (LIF)
• Neuromorphic Inference