Forbench: Symbolic Simulation Helps Make Your Testbench More Formal

πŸ“… 2026-08-02
πŸ“ˆ Citations: 0
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πŸ€– AI Summary
Traditional simulation struggles to cover rare corner-case scenarios, while formal verification is hindered by limited scalability and high usability barriers. To address these challenges, this work proposes Forbenchβ€”a word-level symbolic simulation framework that seamlessly integrates symbolic execution into conventional RTL simulation workflows. By leveraging an SMT solver to support symbolic signals and state transitions, Forbench enables systematic exploration of design behaviors while preserving the semantics of traditional simulation. It further provides a simulation-like Python interface for defining constraints, enabling co-simulation, and performing property checking. Forbench significantly improves verification efficiency without compromising coverage and substantially lowers the barrier to adopting formal methods.
πŸ“ Abstract
Simulation remains the dominant approach in pre-silicon verification due to its ease of deployment and intuitive workflow. However, as simulation only explores a limited subset of possible execution traces within feasible time budgets, it often fails to explore rare corner cases, leaving latent bugs undetected. In contrast, formal verification offers mathematically rigorous guarantees of correctness. However, its practical adoption is constrained, not only by the scalability challenges over large-scale designs, but also by the change of mindset from stimulus-driven operations to the sequence-centric axiomatic view of design behaviors, introducing extra difficulty of writing precise properties to capture the exact verification intent. This paper aims to lower the barrier of applying formal methods in verification, by making simulation "more formal." It introduces Forbench, a word-level symbolic simulation framework that retains the familiar execution semantics of simulation but augments it with solver-backed symbolic signals and state transitions, enabling systematic exploration of RTL behaviors under symbolic inputs and conditions. It offers a Python interface, similar to the existing simulation-based frameworks, for defining constraints, coordinating symbolic (co-)simulations, and performing property checks. In additional to this more accessible interface, experiments also show that Forbench achieves notably speed-up over prior symbolic methods without the loss of coverage.
Problem

Research questions and friction points this paper is trying to address.

formal verification
simulation
symbolic simulation
pre-silicon verification
testbench
Innovation

Methods, ideas, or system contributions that make the work stand out.

symbolic simulation
formal verification
testbench
RTL verification
solver-backed
Z
Ziyi Yang
The Hong Kong University of Science and Technology (Guangzhou)
W
Wenbin Che
The Hong Kong University of Science and Technology (Guangzhou)
Z
Ziyue Zheng
The Hong Kong University of Science and Technology (Guangzhou)
G
Guangyu Hu
The Hong Kong University of Science and Technology
Hongce Zhang
Hongce Zhang
Hong Kong University of Science and Technology (Guangzhou)
Logic Design & VerificationHardware Model Checking