🤖 AI Summary
Accurately predicting hardware failures in large-scale high-performance computing (HPC) systems remains challenging. This study leverages seven years of production logs from the Theta supercomputer to systematically investigate, for the first time, how temporal characteristics of hardware errors—such as regularity and burstiness—critically influence prediction performance. By comparing deep learning models, including LSTM and Transformer, against classical statistical methods and incorporating temporal feature engineering, the authors demonstrate that deep learning approaches excel on error sequences exhibiting structural stability and strong periodicity, whereas sparse, bursty errors remain difficult to predict accurately. The findings provide empirical insights and methodological guidance for advancing fault prediction in HPC environments.
📝 Abstract
Hardware error logs in high-performance computing (HPC) systems provide early signals of abnormal behavior, yet there remain challenges in effectively forecasting these errors using modern predictive methods. This work investigates the boundaries of applying time series forecasting to HPC hardware error dynamics. We use seven years of production logs from the Theta supercomputer to evaluate the predictive efficacy of classical statistical and deep learning models. Our results show that forecasting effectiveness depends strongly on the temporal structure of the error series: regularly occurring and structurally stable errors can be modeled accurately, particularly by LSTM and Transformer architectures with temporal features, while sparse and burst-dominated errors remain difficult to predict. Rather than proposing a deployment-ready failure prediction framework, this study provides empirical guidance on when forecasting is effective and highlights potential directions for improving forecasting accuracy in HPC hardware error analysis.