🤖 AI Summary
Existing 3D FPGA research is hindered by fixed prototypes, limited architectural templates, and purely simulation-based evaluation, impeding practical design exploration. This paper presents the first open-source, end-to-end automated framework for 3D FPGA architecture generation and verification—spanning high-level architectural specification, synthesizable RTL generation, and bitstream compilation. Our method introduces customizable vertical interconnect patterns, a novel 3D switch block, and heterogeneous logic-layer architectures, while integrating physical constraint modeling—including through-silicon via (TSV) density and vertical interconnect delay. A closed-loop workflow integrates high-level modeling, RTL synthesis, bitstream generation, physical feasibility validation, and multi-dimensional quantitative assessment to enable efficient architecture-space exploration. Experimental evaluation across five case studies demonstrates significant improvements in average wirelength, critical-path delay, and routing runtime—validating the framework’s effectiveness, scalability, and physical realizability.
📝 Abstract
While 3D IC technology has been extensively explored for ASICs, their application to FPGAs remains limited. Existing studies on 3D FPGAs are often constrained to fixed prototypes, narrow architectural templates, and simulation-only evaluations. In this work, we present LaZagna, the first open-source framework for automated, end-to-end 3D FPGA architecture generation and evaluation. LaZagna supports high-level architectural specification, synthesizable RTL generation, and bitstream production, enabling comprehensive validation of 3D FPGA designs beyond simulation. It significantly broadens the design space compared to prior work by introducing customizable vertical interconnect patterns, novel 3D switch block designs, and support for heterogeneous logic layers. The framework also incorporates practical design constraints such as inter-layer via density and vertical interconnect delay. We demonstrate the capabilities of LaZagna by generating synthesizable RTL that can be taken through full physical design flows for fabric generation, along with functionally correct bitstreams. Furthermore, we conduct five case studies that explore various architectural parameters and evaluate their impact on wirelength, critical path delay, and routing runtime. These studies showcase the framework's scalability, flexibility, and effectiveness in guiding future 3D FPGA architectural and packaging decisions. LaZagna is fully open-source and available on GitHub.