Overcoming Quadratic Hardware Scaling for a Fully Connected Digital Oscillatory Neural Network

2025-04-29

AI Summary

To address the quadratic hardware resource scaling bottleneck of fully connected digital oscillatory neural networks (ONNs), this paper proposes a hybrid coupling architecture with near-linear (~1.2-order) scalability. The architecture synergistically integrates serialization and parallelization mechanisms, enabling the largest reported hardware implementation of a fully connected digital ONN—comprising 506 oscillators—on a Xilinx Zynq-7020 FPGA. Employing 5-bit coupling weights and 4-bit phase quantization, it achieves high computational fidelity while substantially reducing resource overhead. Compared to conventional recursive architectures, the proposed design increases oscillator count by 10.5× and reduces logic resource utilization by ~62%. Experimental results demonstrate the hardware feasibility of large-scale digital ONNs and establish a scalable circuit paradigm for high-throughput, energy-efficient neuromorphic computing.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Computing with coupled oscillators or oscillatory neural networks (ONNs) has recently attracted a lot of interest due to their potential for massive parallelism and energy-efficient computing. However, to date, ONNs have primarily been explored either analytically or through analog circuit implementations. This paper shifts the focus to the digital implementation of ONNs, examining various design architectures. We first report on an existing digital ONN design based on a recurrent architecture. The major challenge for scaling such recurrent architectures is the quadratic increase in coupling hardware with the network size. To overcome this challenge, we introduce a novel hybrid architecture that balances serialization and parallelism in the coupling elements that shows near-linear hardware scaling, on the order of about 1.2 with the network size. Furthermore, we evaluate the benefits and costs of these different digital ONN architectures in terms time to solution and resource usage on FPGA emulation. The proposed hybrid architecture allows for a 10.5$ imes$ increase in the number of oscillators while using 5-bits to represent the coupling weights and 4-bits to represent the oscillator phase on a Zynq-7020 FPGA board. The near-linear scaling is a major step towards implementing large scale ONN architectures. To the best of our knowledge, this work presents the largest fully connected digital ONN architecture implemented thus far with a total of 506 fully connected oscillators.

Problem

• Overcoming quadratic hardware scaling in digital ONNs
• Introducing hybrid architecture for near-linear scaling
• Evaluating digital ONN designs for resource efficiency

Innovation

• Hybrid architecture balances serialization and parallelism
• Near-linear hardware scaling with network size
• FPGA emulation with 506 fully connected oscillators