Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field.

2025-04-29

Scientific Reports

AI Summary

This work addresses the high latency of elliptic curve cryptography (ECC) hardware accelerators in high-speed wireless communication. We propose a low-latency FPGA-based scalar multiplication accelerator for the Twisted Edwards curve Edwards25519. Our key innovation is a unified projective coordinate arithmetic unit that simultaneously supports both point addition and point doubling in only 646 clock cycles. The design incorporates optimized modular arithmetic and is implemented on the Xilinx Virtex-5 platform. Evaluated over the 256-bit prime field 𝔽_p, the accelerator achieves a scalar multiplication latency of 1.4 ms at a clock frequency of 117.8 MHz, yielding a throughput of 183.38 kbps. Compared to state-of-the-art implementations, our design delivers significantly lower latency while maintaining high performance and inherent resistance to side-channel attacks due to its unified, regular execution flow.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Distributed Search
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems

Application Category

• Security and Privacy: Large-scale security measurements
• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications

Abstract

The performance of any elliptic curve cryptography hardware accelerator significantly relies on the efficiency of the underlying point multiplication (PM) architecture. This article presents a hardware implementation of field-programmable gate array (FPGA) based modular arithmetic, group operation, and point multiplication unit on the twisted Edwards curve (Edwards25519) over the 256-bit prime field. An original hardware architecture of a unified point operation module in projective coordinates that executes point addition and point doubling within a single module has been developed, taking only 646 clock cycles and ensuring a better security level than conventional approaches. The proposed point multiplication module consumes 1.4 ms time, operating at a maximal clock frequency of 117.8 MHz utilising 164,730 clock cycles having 183.38 kbps throughput on the Xilinx Virtex-5 FPGA platform for 256-bit length of key. The comparative assessment of latency and throughput across various related recent works indicates the effectiveness of our proposed PM architecture. Finally, this high throughput and low latency PM architecture will be a good candidate for rapid data encryption in high-speed wireless communication networks.

Problem

• Efficient FPGA-based twisted Edwards curve cryptography accelerator
• Low-latency point multiplication for secure wireless communication
• Optimized modular arithmetic and group operations for Edwards25519

Innovation

• FPGA-based modular arithmetic for Edwards25519
• Unified point operation module in projective coordinates
• Low latency point multiplication at 117.8 MHz