Technology Category
Planning, Routing, and Scheduling: Optimization of Spatio-temporal SystemsSearch and Optimization: Mixed Discrete/Continuous SearchConstraint Satisfaction and Optimization: Satisfiability
Automated SAR ADC Sizing Using Analytical Equations
🤖 AI Summary
To address the time-consuming, inefficient, and suboptimal manual transistor sizing in SAR ADC design—particularly the difficulty in jointly optimizing performance and power—this paper proposes a fully automated transistor sizing synthesis methodology. Methodologically, it establishes a system-level–local two-tier optimization framework that integrates analytical modeling, dependency-graph-driven topological-order scheduling, knowledge-guided computation, and serialized simulation, enabling, for the first time, an end-to-end analytical mapping from high-level specifications (e.g., SNDR, power, area) to complete transistor dimensions. Its key innovations are a human-in-the-loop-free closed-loop design flow and an interpretable dependency-graph-based scheduling mechanism. Evaluated on two representative SAR ADC topologies, the method strictly satisfies all design constraints while achieving simultaneous high SNDR (>65 dB) and ultra-low power consumption (<100 μW).
Technology Category
Application Category
📝 Abstract
Conventional analog and mixed-signal (AMS) circuit designs heavily rely on manual effort, which is time-consuming and labor-intensive. This paper presents a fully automated design methodology for Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) from performance specifications to complete transistor sizing. To tackle the high-dimensional sizing problem, we propose a dual optimization scheme. The system-level optimization iteratively partitions the overall requirements and analytically maps them to subcircuit design specifications, while local optimization loops determines the subcircuits' design parameters. The dependency graph-based framework serializes the simulations for verification, knowledge-based calculations, and transistor sizing optimization in topological order, which eliminates the need for human intervention. We demonstrate the effectiveness of the proposed methodology through two case studies with varying performance specifications, achieving high SNDR and low power consumption while meeting all the specified design constraints.
Problem
Research questions and friction points this paper is trying to address.
Automates SAR ADC design to reduce manual effort
Solves high-dimensional sizing via dual optimization
Ensures performance with dependency graph framework
Innovation
Methods, ideas, or system contributions that make the work stand out.
Automated SAR ADC sizing using analytical equations
Dual optimization scheme for high-dimensional sizing
Dependency graph-based framework for serialized simulations
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