🤖 AI Summary
Current digital compute-in-memory (CIM) accelerators lack an end-to-end design framework supporting capacity-constrained modeling and hardware-software co-optimization. To address this, we propose the first capacity-aware CIM instruction set architecture (ISA) along with a dedicated compilation flow that jointly incorporates fine-grained data partitioning, parallel scheduling, and architecture-algorithm co-optimization. Our framework unifies a configurable ISA, a domain-specific compiler, and a cycle-accurate CIM simulator—enabling automated mapping and holistic hardware-software co-modeling. It facilitates rapid prototyping across diverse architectural configurations and enables system-level performance and energy-efficiency evaluation on mainstream DNN models. Experimental results demonstrate significantly improved design space exploration efficiency. This work establishes a foundational infrastructure for the efficient development and optimization of digital CIM accelerators.
📝 Abstract
Digital Compute-in-Memory (CIM) architectures have shown great promise in Deep Neural Network (DNN) acceleration by effectively addressing the"memory wall"bottleneck. However, the development and optimization of digital CIM accelerators are hindered by the lack of comprehensive tools that encompass both software and hardware design spaces. Moreover, existing design and evaluation frameworks often lack support for the capacity constraints inherent in digital CIM architectures. In this paper, we present CIMFlow, an integrated framework that provides an out-of-the-box workflow for implementing and evaluating DNN workloads on digital CIM architectures. CIMFlow bridges the compilation and simulation infrastructures with a flexible instruction set architecture (ISA) design, and addresses the constraints of digital CIM through advanced partitioning and parallelism strategies in the compilation flow. Our evaluation demonstrates that CIMFlow enables systematic prototyping and optimization of digital CIM architectures across diverse configurations, providing researchers and designers with an accessible platform for extensive design space exploration.