Efficient Optimization Accelerator Framework for Multistate Ising Problems

📅 2025-05-26
📈 Citations: 0
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🤖 AI Summary
Conventional QUBO modeling for polymorphic Ising problems causes exponential solution-space expansion and degraded solution quality. Method: We propose a generalized Boolean logic modeling framework that directly encodes polymorphic spin interactions—bypassing QUBO conversion—and achieve, for the first time, deep synergy between parallel annealing and probabilistic Ising solvers. We further design a dedicated 1024-neuron fully connected accelerator optimized for energy efficiency, silicon area, and solution quality. Results: On graph coloring benchmarks, our approach matches state-of-the-art heuristic and machine learning methods in accuracy, reduces error rate by 50% versus conventional Ising formulations, achieves a 10⁴× speedup, and cuts physical neuron requirements by 1.5–4×—surpassing all existing approaches across all key metrics.

Technology Category

Machine Learning: Probabilistic Circuits and Graphical ModelsConstraint Satisfaction and Optimization: SatisfiabilityKnowledge Representation and Reasoning: Computational Complexity of Reasoning

Application Category

Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphsSemantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMsSearch and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
📝 Abstract
Ising Machines are a prominent class of hardware architectures that aim to solve NP-hard combinatorial optimization problems. These machines consist of a network of interacting binary spins/neurons that evolve to represent the optimum ground state energy solution. Generally, combinatorial problems are transformed into quadratic unconstrained binary optimization (QUBO) form to harness the computational efficiency of these Ising machines. However, this transformation, especially for multi-state problems, often leads to a more complex exploration landscape than the original problem, thus severely impacting the solution quality. To address this challenge, we model the spin interactions as a generalized boolean logic function to significantly reduce the exploration space. We benchmark the graph coloring problem from the class of multi-state NP-hard optimization using probabilistic Ising solvers to illustrate the effectiveness of our framework. The proposed methodology achieves similar accuracy compared to state-of-the-art heuristics and machine learning algorithms, and demonstrates significant improvement over the existing Ising methods. Additionally, we demonstrate that combining parallel tempering with our existing framework further reduces the coloring error by up to 50% compared to the conventionally used Gibbs sampling algorithm. We also design a 1024-neuron all-to-all connected probabilistic Ising accelerator that shows up to 10000x performance acceleration compared to heuristics while reducing the number of required physical neurons by 1.5-4x compared to conventional Ising machines. Indeed, this accelerator solution demonstrates improvement across all metrics over the current methods, i.e., energy, performance, area, and solution quality. Thus, this work expands the potential of existing Ising hardware to solve a broad class of these multistate optimization problems.
Problem

Research questions and friction points this paper is trying to address.

Reducing exploration space in multistate Ising problems
Improving solution quality for NP-hard optimization problems
Accelerating performance of Ising machines for combinatorial optimization
Innovation

Methods, ideas, or system contributions that make the work stand out.

Generalized boolean logic reduces exploration space
Parallel tempering cuts coloring error by 50%
1024-neuron accelerator boosts performance 10000x
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Chirag Garg
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720, USA
Sayeef Salahuddin
Sayeef Salahuddin
TSMC Distinguished Professor of EECS, University of California, Berkeley
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