Verification of Compiler-to-Accelerator Mappings for Machine Learning Accelerators

2026-09-24

AI Summary

This study addresses the functional mismatches arising from the lack of hardware-level verification in compilation mappings for machine learning accelerators. To this end, it proposes BOLT, a formal verification framework that aligns loop structures with associated data layouts. Notably, BOLT introduces the first coarse-grained intrinsic verification method that operates without requiring additional auxiliary information. Furthermore, by leveraging synchronization skeleton and layout sketch template techniques, the framework achieves end-to-end correctness proofs for compiler-to-accelerator mappings. The prototype system successfully verifies the correctness of complex compilation mappings on two open-source ML accelerators, thereby providing a reliable foundation for hardware-software co-design.

Abstract

To meet the performance needs of modern machine learning (ML) applications, ML compiler frameworks support compiler-to-accelerator mappings that offload parts of application code to operations in specialized hardware accelerators. However, most of these frameworks do not verify these mappings down to the hardware level, potentially resulting in functional mismatches. In this paper we propose BOLT, the first framework for formally verifying the correctness of compiler-to-accelerator mappings for coarse-grained intrinsics in ML accelerators, with respect to a formal hardware semantics. BOLT does not require additional information from the compiler, and verifies the functional equivalence of the application code and the code for the mapped hardware accelerator intrinsic, including handling of complex loop nests and tensor data layouts in hardware. It effectively utilizes a pattern of *aligning* software loops with the hardware, followed by *relating* corresponding data layouts, to enable verification using well-aligned product programs. To support these steps, we propose two custom templates --- the sync-skeleton and the layout-sketch --- to guide users in aligning loops and specifying data layout relationships, respectively. We have developed a proof-of-concept prototype for BOLT and use it to successfully verify the correctness of several complex mappings for two recent open-source ML accelerators.

Problem

• Machine Learning Accelerators
• Compiler-to-Accelerator Mappings
• Formal Verification
• Functional Equivalence

Innovation

• formal verification
• ML accelerators
• compiler-to-accelerator mappings
• product programs
• tensor data layouts