Problem
Research questions and friction points this paper is trying to address.
Analog circuit yield optimization
Process variation
Monte Carlo simulation
Simulation efficiency
Zeroth-order optimization
Simulation-Efficient Analog Circuit Yield Optimization via Monte Carlo Zeroth-Order Gradient Estimation
🤖 AI Summary
This study addresses the prohibitive cost of Monte Carlo simulations and the absence of gradients for discrete objective functions in analog circuit yield optimization by proposing ZO-MC-SGD, a black-box optimization method. By leveraging shared samples to estimate descent directions under design perturbations, this approach converts continuous specification margins into stochastic gradients, eliminating the need for SPICE-based differentiation or global surrogate modeling. Theoretical analysis establishes the unbiasedness and variance bounds of the gradient estimator, removing explicit dependence on process dimensionality. Evaluated across five benchmark circuits, the proposed method achieves an average yield of 0.95 while reducing the simulation budget by up to eightfold compared with the strongest baseline.
📝 Abstract
Yield optimization under process variation is expensive because each candidate design must be evaluated across many Monte Carlo SPICE samples. The resulting finite-sample yield is also piecewise constant in the design parameters, providing little local information for optimization. We introduce zeroth-order Monte Carlo stochastic gradient descent (ZO-MC-SGD), a black-box method that converts continuous specification margins into stochastic descent directions. Each update evaluates opposite design perturbations under shared process samples, allowing a small simulation batch to estimate a local direction without differentiating SPICE or fitting a global surrogate model. A Spearman rank-correlation test checks that the margin-based loss orders designs consistently with empirical yield. We prove that the estimator is unbiased for a Gaussian-smoothed surrogate and derive variance and sample-complexity bounds with no explicit dependence on process dimension. Across five analog circuit benchmarks with up to 30 design variables and 42 process variables, ZO-MC-SGD reaches a mean yield of 0.95 on four circuits within 50--200 simulations and the empirical yield ceiling on the fifth. Relative to the best of five black-box and learning-based baselines, it reduces the required simulation budget by up to a factor of eight.
Innovation
Methods, ideas, or system contributions that make the work stand out.
Zeroth-order optimization
Monte Carlo stochastic gradient descent
Analog circuit yield optimization
Black-box optimization
Simulation efficiency
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