The Power of Indirection: Scaling Switches Beyond Silicon Boundaries

2026-09-25

AI Summary

This work proposes Fastroute, a novel architecture addressing interconnect bandwidth bottlenecks and single-chip area limitations in multi-ASIC switches. Fastroute introduces an indirect layer that uniquely integrates packet and circuit switching, leveraging dynamic port remapping to localize traffic and substantially reduce cross-ASIC communication demands. A hardware prototype is developed and systematically evaluated using large language model training workloads. Experimental results demonstrate that Fastroute closely approximates single-ASIC performance while significantly reducing bandwidth overhead and power consumption. Furthermore, it effectively liberates external interface capacity to satisfy high-radix networking requirements, enabling system scalability without reliance on next-generation ASICs.

Abstract

The slowdown of Moore's law and the area limit of monolithic integration have made chiplet-based designs inevitable across many domains, including network ASICs. However, combining multiple network ASICs together poses a fundamental challenge: maintaining sufficient inter-ASIC bandwidth to match the performance of an idealistic single-ASIC design. Providing full bandwidth is prohibitively expensive as it requires valuable forwarding capacity, while reducing inter-ASIC bandwidth creates severe performance bottlenecks. We propose a novel multi-ASIC switch architecture that introduces a circuit-switched indirection layer in front of the ASICs. This layer flexibly remaps ingress ports across ASICs, localizing traffic and minimizing inter-ASIC communication based on observed patterns. Our system, Fastroute, combines packet and circuit switching to deliver performance comparable to a single-ASIC switch while reducing inter-ASIC bandwidth requirements. This frees up capacity for external network interfaces, allowing Fastroute to outperform traditional non-oversubscribed multi-ASIC designs. Our hardware prototype demonstrates the system's functional feasibility by evaluating it on an LLM training workload. By reducing bandwidth and power overhead, Fastroute bridges the gap between silicon fabrication limits and soaring application demands. It provides an efficient transition to multi-ASIC switches, enabling bandwidth and radix demand to be met without waiting for the next ASIC generation.

Problem

• multi-ASIC switch
• inter-ASIC bandwidth
• chiplet-based design
• Moore's law slowdown
• network ASIC

Innovation

• Multi-ASIC Switch
• Circuit-Switched Indirection
• Packet-Circuit Hybrid Switching
• Chiplet Architecture
• Traffic Localization