GNN-based Path-aware multi-view Circuit Learning for Technology Mapping

2026-01-14

arXiv.org

AI Summary

该研究通过引入基于图神经网络的路径感知多视图电路学习框架GPA，解决了传统技术映射中由于依赖抽象延迟模型导致的延迟估计不准确问题。

Abstract

Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nuanced timing behavior behavior of real post-mapping circuits. To address this fundamental limitation, we introduce GPA(graph neural network (GNN)-based Path-Aware multi-view circuit learning), a novel GNN framework that learns precise, data-driven delay predictions by synergistically fusing three complementary views of circuit structure: And-Inverter Graphs (AIGs)-based functional encoding, post-mapping technology emphasizes critical timing paths. Trained exclusively on real cell delays extracted from critical paths of industrial-grade post-mapping netlists, GPA learns to classify cut delays with unprecedented accuracy, directly informing smarter mapping decisions. Evaluated on the 19 EPFL combinational benchmarks, GPA achieves 19.9%, 2.1% and 4.1% average delay reduction over the conventional heuristics methods (techmap, MCH) and the prior state-of-the-art ML-based approach SLAP, respectively-without compromising area efficiency.

Problem

• technology mapping
• delay estimation
• circuit learning

Innovation

• GNN-based Path-Aware multi-view circuit learning
• data-driven delay predictions
• And-Inverter Graphs (AIGs)
• critical timing paths
• cut delays