Circuit-Architecture-Training Co-Design with Regenerative-SA Similarity Sensing for Aggressive SAR Skipping in Analog Compute-in-Memory

2026-09-21

AI Summary

本文提出了一种通过检测放大器再生来减少CIM系统中SAR比较次数的电路-架构-训练协同设计框架，从而降低能耗。

Abstract

This work presents a circuit-architecture-training co-design framework that exploits sense-amplifier (SA) regeneration to detect analog-output similarity and reduce SAR comparisons in compute-in-memory (CIM) systems. Hardware-aware training incorporates circuit-characterized SA disturbance and encoding errors caused by prefix reuse, enabling aggressive comparison skipping. The detector is characterized through 55-nm CMOS schematic simulations, with system-level evaluation on WRN-28-10, ResNet20, and DeiT using an ISAAC-based W4A4 CIM model. On WRN-28-10, the proposed approach achieves 77.3% Top-1 accuracy (W4A4 baseline: 78.4%) while reducing SAR comparisons by 48.19% across the evaluated layers. Energy-budget analysis estimates a 27.18% reduction in reference ADC energy after detector overhead, leaving 0.52 pJ per conversion to accommodate additional control and peripheral costs.

Problem

• compute-in-memory
• SAR comparisons
• energy efficiency

Innovation

• circuit-architecture-training co-design
• sense-amplifier regeneration
• SAR comparison skipping
• compute-in-memory (CIM)
• hardware-aware training