Technology Category
Machine Learning: Hardware-aware MLComputer Vision: Motion & TrackingIntelligent Robots: Multimodal Perception & Sensor Fusion
High Throughput Event Filtering: The Interpolation-based DIF Algorithm Hardware Architecture
🤖 AI Summary
Event camera data streams are highly susceptible to illumination and temperature variations, generating high-throughput, non-stationary noise that demands real-time, robust denoising. To address this, we propose DIF—a synthesizable, high-throughput hardware filter architecture integrating distance-weighted interpolation with a frequency-adaptive weighting mechanism, coupled with a customized event-stream pipeline. DIF is the first FPGA implementation enabling real-time denoising of 1280×720 high-resolution event streams at 403.39 MEPS. We further introduce the first publicly available high-resolution event denoising benchmark dataset. Evaluated across a wide noise spectrum, DIF achieves AUROC scores of 0.844–0.999, substantially outperforming existing methods. Our core contributions are: (1) the first synthesizable DIF hardware architecture; (2) the first high-resolution event denoising benchmark; and (3) a real-time filtering solution uniquely combining high throughput with strong robustness to non-stationary noise.
Technology Category
Application Category
📝 Abstract
In recent years, there has been rapid development in the field of event vision. It manifests itself both on the technical side, as better and better event sensors are available, and on the algorithmic side, as more and more applications of this technology are proposed and scientific papers are published. However, the data stream from these sensors typically contains a significant amount of noise, which varies depending on factors such as the degree of illumination in the observed scene or the temperature of the sensor. We propose a hardware architecture of the Distance-based Interpolation with Frequency Weights (DIF) filter and implement it on an FPGA chip. To evaluate the algorithm and compare it with other solutions, we have prepared a new high-resolution event dataset, which we are also releasing to the community. Our architecture achieved a throughput of 403.39 million events per second (MEPS) for a sensor resolution of 1280 x 720 and 428.45 MEPS for a resolution of 640 x 480. The average values of the Area Under the Receiver Operating Characteristic (AUROC) index ranged from 0.844 to 0.999, depending on the dataset, which is comparable to the state-of-the-art filtering solutions, but with much higher throughput and better operation over a wide range of noise levels.
Problem
Research questions and friction points this paper is trying to address.
Filters noise from high-throughput event vision sensors
Proposes hardware architecture for DIF algorithm on FPGA
Evaluates performance with new high-resolution event dataset
Innovation
Methods, ideas, or system contributions that make the work stand out.
FPGA-based DIF filter hardware architecture
High-throughput event noise filtering
New high-resolution event dataset
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