ARM SVE Unleashed: Performance and Insights Across HPC Applications on Nvidia Grace

2025-05-14

AI Summary

ARM Scalable Vector Extension (SVE) lacks a quantitative evaluation framework for vectorization efficiency in high-performance computing (HPC) applications on NVIDIA Grace platforms, hindering production readiness assessment. Method: We propose a length-element-coupled enhanced Roofline model, introduce the first quantitative metric for SVE vectorization benefit, and develop the first decision-tree classifier to assess HPC application acceleration potential on SVE. Using SVE code analysis, performance monitoring unit (PMU) event sampling, and analytical modeling, we precisely identify vectorization bottlenecks. Contribution/Results: Experiments across representative HPC workloads show an average 37% reduction in total instruction count and up to 2.1× speedup in critical kernels. The study validates SVE’s production readiness for HPC deployment on Grace and establishes a reusable methodology for ARM architecture–based high-performance optimization.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Learning & Optimization for CV
• Search and Optimization: Evaluation and Analysis

Application Category

• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Security and Privacy: Large-scale security measurements

Abstract

Vector architectures are essential for boosting computing throughput. ARM provides SVE as the next-generation length-agnostic vector extension beyond traditional fixed-length SIMD. This work provides a first study of the maturity and readiness of exploiting ARM and SVE in HPC. Using selected performance hardware events on the ARM Grace processor and analytical models, we derive new metrics to quantify the effectiveness of exploiting SVE vectorization to reduce executed instructions and improve performance speedup. We further propose an adapted roofline model that combines vector length and data elements to identify potential performance bottlenecks. Finally, we propose a decision tree for classifying the SVE-boosted performance in applications.

Problem

• Evaluating ARM SVE maturity for HPC applications
• Quantifying SVE vectorization impact on instruction reduction
• Identifying performance bottlenecks via adapted roofline model

Innovation

• Utilizes ARM SVE for HPC vectorization efficiency
• Introduces metrics for SVE instruction reduction
• Proposes adapted roofline model for bottlenecks