🤖 AI Summary
To address high power consumption, inflexible instruction sets, and difficulties in integrating domain-specific accelerators in edge-computing embedded systems, this work designs and implements a heterogeneous SoC based on the RISC-V RV32I+M+A ISA, incorporating a tightly coupled, custom DSP accelerator. Leveraging RISC-V’s modular ISA, we propose a software–hardware co-optimization architecture that enables instruction-level and microarchitectural-level coordination while preserving full standard compliance. The design employs cycle-accurate simulation and RTL-level integration, combined with low-power circuit techniques. Under identical process technology, it achieves a 17% reduction in dynamic power versus the ARM Cortex-M0 and a significant reduction in CPI. Our key contribution is the first lightweight, tightly coupled accelerator microarchitecture specifically tailored for edge-oriented DSP workloads—demonstrating, for the first time, simultaneous improvements in energy efficiency and real-time performance for RISC-V-based heterogeneous SoCs.
📝 Abstract
This paper presents a comprehensive analysis of the RISC-V instruction set architecture, focusing on its modular design, implementation challenges, and performance characteristics. We examine the RV32I base instruction set with extensions for multiplication (M) and atomic operations (A). Through cycle-accurate simulation of a pipelined implementation, we evaluate performance metrics including CPI (cycles per instruction) and power efficiency. Our results demonstrate RISC-V's advantages in embedded systems and its scalability for custom accelerators. Comparative analysis shows a 17% reduction in power consumption compared to ARM Cortex-M0 implementations in similar process nodes. The open-standard nature of RISC-V provides significant flexibility for domain-specific optimizations.