AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security

2025-05-17

AI Summary

To address the limitations of existing AES hardware accelerators in embedded and IoT applications—particularly concerning latency, energy efficiency, and configurability—this paper proposes a low-latency AES instruction-set extension accelerator tailored for the RISC-V architecture. The design introduces three key innovations: (1) a high-bandwidth on-die buffer architecture to minimize memory access latency; (2) a custom AES-specific instruction set enabling fine-grained control over cryptographic operations; and (3) a ping-pong DMA pipelining mechanism to sustain continuous data flow. The accelerator supports all standard AES modes (ECB, CBC, CTR, etc.) and key lengths (128-, 192-, and 256-bit) with real-time encryption/decryption capability. Implemented on a Xilinx ZCU102 FPGA, it achieves up to 255.97× higher throughput and 453.04× better energy efficiency compared to general-purpose CPU/GPU baselines. Moreover, its area-normalized throughput outperforms state-of-the-art AES accelerators.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Philosophy and Ethics of AI: Privacy & Security

Application Category

• Security and Privacy: Applications of cryptography
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

The Advanced Encryption Standard (AES) is a widely adopted cryptographic algorithm essential for securing embedded systems and IoT platforms. However, existing AES hardware accelerators often face limitations in performance, energy efficiency, and flexibility. This paper presents AES-RV, a hardware-efficient RISC-V accelerator featuring low-latency AES instruction extensions optimized for real-time processing across all AES modes and key sizes. AES-RV integrates three key innovations: high-bandwidth internal buffers for continuous data processing, a specialized AES unit with custom low-latency instructions, and a pipelined system supported by a ping-pong memory transfer mechanism. Implemented on the Xilinx ZCU102 SoC FPGA, AES-RV achieves up to 255.97 times speedup and up to 453.04 times higher energy efficiency compared to baseline and conventional CPU/GPU platforms. It also demonstrates superior throughput and area efficiency against state-of-the-art AES accelerators, making it a strong candidate for secure and high-performance embedded systems.

Problem

• Enhancing AES performance for IoT security
• Overcoming energy and flexibility limitations in AES accelerators
• Optimizing real-time AES processing across all modes

Innovation

• Low-latency AES instruction extensions for RISC-V
• High-bandwidth internal buffers for continuous processing
• Pipelined system with ping-pong memory transfer