6G communications through sub-Terahertz CMOS power amplifiers: Design challenges and trends
🤖 AI Summary
The emerging 6G communication standard demands sub-terahertz (300–400 GHz) CMOS power amplifiers (PAs) with high efficiency, output power, and robustness—challenging due to severe parasitic effects and frequency limitations in conventional CMOS designs.
Method: This project proposes the first multi-physics coupled design framework for sub-THz CMOS PAs, integrating electromagnetic, thermal, and nonlinear device modeling. It introduces a novel methodology for quantifying process-variation robustness, establishes a scalable mmWave-to-THz cross-band PA design paradigm, and incorporates broadband matching network synthesis, dynamic bias control, and on-chip harmonic suppression.
Contribution/Results: Implemented in ≥28 nm CMOS, the PA achieves a peak power-added efficiency of 18.5% and an output power of 13 dBm at 300–400 GHz. This represents a significant advancement in 6G RF front-end performance and provides critical enabling technology for prototype system development.
Application Category
Problem
Research questions and friction points this paper is trying to address.
Overcoming 5G limitations for AI, VR, and digital twins with 6G sub-THz tech
Designing efficient CMOS power amplifiers for sub-THz 6G communications
Comparing PA architectures and optimization techniques for better performance
Innovation
Methods, ideas, or system contributions that make the work stand out.
Sub-THz CMOS power amplifiers for 6G
Circuit optimization techniques for PA
Scaling down CMOS to break frequency limits
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