Arbiter PUF: Uniqueness and Reliability Analysis Using Hybrid CMOS-Stanford Memristor Model

📅 2025-07-06
📈 Citations: 0
✨ Influential: 0
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🤖 AI Summary
To address physical attacks and hardware cloning threats against IoT devices in third-party foundry environments, this paper proposes a novel Arbiter PUF architecture leveraging the Stanford memristor model. The design uniquely exploits the intrinsic stochasticity of filament evolution in memristors to enhance response reliability and resistance to modeling attacks. A co-modeling framework based on 45-nm CMOS technology is employed, integrating Monte Carlo simulations and Hamming distance analysis to rigorously evaluate uniqueness and stability under process variations, temperature fluctuations, and supply voltage deviations. Experimental results demonstrate that the memristor-based PUF achieves significantly higher reliability than conventional CMOS PUFs; while uniqueness shows room for further optimization, the architecture validates the efficacy of memristors in realizing robust hardware security primitives and highlights their practical potential for secure IoT authentication.

Technology Category

Machine Learning: Hardware-aware MLCognitive Modeling & Cognitive Systems: Agent ArchitecturesComputer Vision: Adversarial Attacks & Robustness

Application Category

Security and Privacy: Large-scale security measurementsUser Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systemsSystems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
📝 Abstract
In an increasingly interconnected world, protecting electronic devices has grown more crucial because of the dangers of data extraction, reverse engineering, and hardware tampering. Producing chips in a third-party manufacturing company can let hackers change the design. As the Internet of Things (IoT) proliferates, physical attacks happen more, and conventional cryptography techniques do not function well. In this paper, we investigate the design and assessment of PUFs using the Stanford Memristor Model, utilizing its random filament evolution to improve security. The system was built using 45nm CMOS technology. A comparison is made between CMOS-based and memristor-based Arbiter PUFs, evaluating their performance under temperature, voltage, and process variations. Intra- and inter-hamming distances are employed by Monte Carlo simulations to estimate uniqueness and reliability. The results show that memristor-based PUFs offer better reliability than CMOS-based designs, though uniqueness needs further improvement. Furthermore, this study sheds light on the reasonableness of memristor-based PUFs for secure applications in hardware security.
Problem

Research questions and friction points this paper is trying to address.

Analyzing security risks in third-party chip manufacturing
Comparing CMOS and memristor PUFs for hardware security
Evaluating PUF reliability and uniqueness under environmental variations
Innovation

Methods, ideas, or system contributions that make the work stand out.

Hybrid CMOS-Stanford Memristor Model enhances security
45nm CMOS technology for PUF implementation
Monte Carlo simulations assess uniqueness and reliability
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T
Tanvir Rahman
Dept. of EEE, BUET, Dhaka, Bangladesh
A
A. B. M. Harun-ur Rashid
Dept. of EEE, BUET, Dhaka, Bangladesh