Effective Capacitance Modeling Using Graph Neural Networks

2025-07-04

AI Summary

Accurate post-placement effective capacitance (Ceff) modeling is critical for static timing analysis (STA) in VLSI design; however, conventional approaches rely on routing information or heuristic approximations, suffering from low accuracy and high computational overhead. This paper proposes GNN-Ceff—the first graph neural network method tailored for post-placement Ceff prediction. It encodes the circuit netlist and physical placement coordinates into a heterogeneous graph and learns capacitance distribution patterns end-to-end. Leveraging GPU parallelization, GNN-Ceff achieves 929× speedup over the best prior baseline on real industrial benchmarks while improving prediction accuracy—reducing mean absolute error by 37%. Crucially, it enables high-confidence timing pre-evaluation without requiring routing information, thereby facilitating layout-timing co-optimization and supporting robust early-stage design decisions.

Technology Category

Machine Learning: Hardware-aware MLPlanning, Routing, and Scheduling: Optimization of Spatio-temporal SystemsComputer Vision: Generative Adversarial Networks (GANs) for Vision

Application Category

Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphsSemantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMsWeb Mining and Content Analysis: Robustness and generalizability of Web mining methods

Abstract

Static timing analysis is a crucial stage in the VLSI design flow that verifies the timing correctness of circuits. Timing analysis depends on the placement and routing of the design, but at the same time, placement and routing efficiency depend on the final timing performance. VLSI design flows can benefit from timing-related prediction to better perform the earlier stages of the design flow. Effective capacitance is an essential input for gate delay calculation, and finding exact values requires routing or routing estimates. In this work, we propose the first GNN-based post-layout effective capacitance modeling method, GNN-Ceff, that achieves significant speed gains due to GPU parallelization while also providing better accuracy than current heuristics. GNN-Ceff parallelization achieves 929x speedup on real-life benchmarks over the state-of-the-art method run serially.

Problem

• Modeling effective capacitance for VLSI timing analysis
• Improving accuracy and speed in capacitance prediction
• Using GNNs to replace traditional heuristic methods

Innovation

• GNN-based post-layout capacitance modeling
• GPU parallelization for speed gains
• Better accuracy than current heuristics