SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput

2026-07-20

AI Summary

Traditional tightly coupled RISC-V vector processors struggle to sustain high-throughput execution due to bottlenecks in instruction supply, scalar latency, and dependency handling. This work proposes SEAM-V, a novel architecture that decouples computation at the task level, employs localized instruction delivery, and generates VLIW-style execution packet (EP) streams. By explicitly maintaining EP context in the backend, SEAM-V enables intra-packet hazard suppression and prefetching. The design integrates hybrid decoupled scheduling, EP serialization, request-bound prefetching, and dynamic resource management to preserve dynamic dependency and memory ordering correctness while enabling intra-packet optimizations and limited inter-packet vector overlap. Evaluated on 17 representative kernels, SEAM-V achieves a geometric mean speedup of 1.34× over Ara, with near 3× acceleration on one-dimensional variable-length vector kernels at AVL=32.

Abstract

Data-parallel workloads in deep learning and scientific computing continue to drive demand for higher processor throughput, energy efficiency, and scalability. The RISC-V Vector Extension (RVV) supports scalable execution through a vector-length-agnostic programming model. However, many tightly coupled implementations still rely on the scalar core to supply vector instructions one at a time, making execution susceptible to vector-instruction supply gaps, scalar-side progression delays, and conservative dependence handling in short-vector, loop-tail, and control/memory-interleaved phases. This paper presents SEAM-V, a hybrid-decoupled vector execution architecture for RVV. SEAM-V forms a continuous stream of execute packets (EPs) through task-level decoupling, local instruction supply, and VLIW-style packing. After an EP is serialized into individual requests, its EP identity and request-bound prefetch context remain visible to the dynamic vector backend, enabling same-EP candidate-hazard suppression and request-bound prefetching. The hybrid-dispatch path can also provide limited cross-EP vector overlap when the required safety conditions are satisfied. Cross-EP dependences, dependences not exempted by the EP contract, resource conflicts, and memory ordering remain dynamically managed by the backend. Cycle-accurate RTL evaluation shows that, compared with an Ara-based tightly coupled RVV implementation (TC), SEAM-V achieves a geometric-mean speedup of 1.34x across 17 representative kernels. The one-dimensional variable-AVL, BLAS and matrix, and fixed-size application groups achieve speedups of 1.50x, 1.25x, and 1.27x, respectively. At AVL=32, the geometric-mean speedup across six one-dimensional vector kernels approaches 3x.

Problem

• RISC-V Vector Extension
• vector throughput
• instruction supply gap
• scalar-vector coupling
• execution decoupling

Innovation

• hybrid-decoupled architecture
• execute packet (EP)
• backend-visible context
• vector throughput
• RISC-V Vector Extension