Hardware Mechanisms to Dynamically Throttle AI Performance

2026-07-20

AI Summary

This work addresses the lack of dynamic, fine-grained performance throttling mechanisms for AI workloads at the hardware level, where existing software-based defenses are easily bypassed and prior hardware approaches offer only coarse-grained control. The paper proposes a runtime GPU memory subsystem throttling mechanism based on microarchitectural control knobs, enabling architectural-level, fine-grained, and dynamic AI performance suppression for the first time. By orchestrating primitives such as cache way masking, credit-based rate limiting, latency injection, and bank arbitration, the approach jointly regulates L2 cache capacity, latency, bandwidth, and shared memory port access rates. With an overhead of only approximately 10K flip-flops, the mechanism achieves up to 80% performance reduction, stabilizes within 5–80K cycles after throttling initiation, and exerts minimal impact on the rest of the chip.

Abstract

As more capable AI models are increasingly integrated into critical computer systems, the lack of control over AI intent motivates safety mechanisms. Existing software safeguards impose only behavioral constraints that can potentially be bypassed by sufficiently intelligent models. While hardware-level safety enforcement has been recognized as an essential last line of defense, few mechanisms have been proposed beyond policy regulations on unauthorized accesses or coarse full-chip shutdown. What is missing is a fine-grained, dynamic intervention mechanism at the architecture level. In this paper, we introduce a set of microarchitecture knobs which dynamically control the available hardware resources to limit AI performance at runtime. We evaluate candidate knobs spanning the GPU memory subsystem, across capacity, bandwidth, latency and frequency dimensions, and narrow down to four strong candidates: L2 size, L2 latency, L2 bandwidth, and shared memory port access rate. To minimize new logic and extra design cost, we build all four mechanisms from well-established microarchitectural primitives: cache way masking, credit-based rate limiting, latency insertion, and bank arbitration. We show that these knobs achieve high performance sensitivity (up to 80% performance cut at 1/8 resource availability), negligible implementation cost (<~10K flip flops), fast stabilization after dynamic throttling (5-80K cycles), and minimal collateral impact on the rest of the chip. Further, multi-knob analysis reveals combinations of knobs that amplify the performance degradation beyond the effect of each knob individually, which enables a broader range of performance targets.

Problem

• AI safety
• hardware throttling
• dynamic control
• microarchitecture
• performance limitation

Innovation

• dynamic throttling
• microarchitectural knobs
• hardware safety mechanisms
• GPU memory subsystem
• performance control