🤖 AI Summary
To address the challenges of escalating power consumption and computation errors induced by device variations in high-row-parallel compute-in-memory (CiM) architectures, this work proposes a low-power, robust multiply-accumulate (MAC) architecture for AI accelerators. We introduce a novel 4T2R ReRAM-based CiM cell—reducing device count by 50% versus conventional 4T4R designs—thereby mitigating process variation impact and lowering write energy. Complementing this, an optimized 8T SRAM-assisted analog-domain accumulation circuit enables precise, high-parallelism summation. Experimental results demonstrate that, while maintaining a 128×128 MAC parallelism scale, the proposed architecture achieves a 2.3× improvement in energy efficiency and reduces computational error rate to 0.8%, significantly enhancing system fault tolerance and operational stability. This work establishes a scalable hardware paradigm for high-reliability CiM accelerators.
📝 Abstract
Computation-in-Memory (CiM) is attracting attention as a technology that can perform MAC calculations required for AI accelerators, at high speed with low power consumption. However, there is a problem regarding power consumption and device-derived errors that increase as row parallelism increases. In this paper, a 4T2R ReRAM cell and an 8T SRAM CiM suitable for CiM is proposed. It is shown that adopting the proposed 4T2R ReRAM cell reduces the errors due to variation in ReRAM devices compared to conventional 4T4R ReRAM cells.