One Step Beyond: Feedthrough & Placement-Aware Rectilinear Floorplanner

2025-07-20

AI Summary

Existing chip floorplanning methods are decoupled from subsequent physical design stages, leading to suboptimal intra-module placement and excessive inter-module feedthroughs. This work proposes a PPA-aware, three-stage orthogonal floorplanning methodology that jointly optimizes intra-module component placement and inter-module through-signal routing for the first time during floorplanning, incorporating variable-shape local refinement and cross-stage feedback. Key techniques include wiremask and position masking, zero-white-space placement, and a fast-tree-search-based co-placement algorithm for macros and standard cells. Experimental results demonstrate a 6% reduction in half-perimeter wirelength (HPWL), 5.16% and 29.15% reductions in feedthrough pins (FTpin) and feedthrough modules (FTmod), respectively, and a 14% improvement in placement quality—significantly enhancing layout awareness and enabling tighter co-optimization of wirelength and feedthroughs.

Technology Category

Planning, Routing, and Scheduling: Optimization of Spatio-temporal SystemsMachine Learning: Hardware-aware MLSearch and Optimization: Distributed Search

Application Category

Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphsSystems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applicationsEconomics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

Floorplanning determines the shapes and locations of modules on a chip canvas and plays a critical role in optimizing the chip's Power, Performance, and Area (PPA) metrics. However, existing floorplanning approaches often fail to integrate with subsequent physical design stages, leading to suboptimal in-module component placement and excessive inter-module feedthrough. To tackle this challenge, we propose Flora, a three-stage feedthrough and placement aware rectilinear floorplanner. In the first stage, Flora employs wiremask and position mask techniques to achieve coarse-grained optimization of HPWL and feedthrough. In the second stage, under the constraint of a fixed outline, Flora achieves a zero-whitespace layout by locally resizing module shapes, thereby performing fine-grained optimization of feedthrough and improving component placement. In the third stage, Flora utilizes a fast tree search-based method to efficiently place components-including macros and standard cells-within each module, subsequently adjusting module boundaries based on the placement results to enable cross-stage optimization. Experimental results show that Flora outperforms recent state-of-the-art floorplanning approaches, achieving an average reduction of 6% in HPWL, 5.16% in FTpin, 29.15% in FTmod, and a 14% improvement in component placement performance.

Problem

• Optimizes chip Power, Performance, and Area (PPA) metrics
• Reduces inter-module feedthrough and improves component placement
• Integrates floorplanning with subsequent physical design stages

Innovation

• Wiremask and position mask for coarse optimization
• Local resizing for zero-whitespace fine optimization
• Tree search-based component placement and boundary adjustment