A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency

2026-03-17

AI Summary

This work addresses the engineering challenges of quantum error correction (QEC)—including real-time control, low-latency decoding, and system integration—by presenting the first fully integrated, open-source QEC platform. Built upon the RISC-V-based quantum control architecture RISC-Q, the system combines real-time superconducting qubit control, distributed multi-board interconnects, and hardware-accelerated decoders on an AMD ZCU216 RFSoC FPGA. The prototype achieves an end-to-end feedback latency of 446 nanoseconds for a distance-3 surface code across a three-board setup. The architecture is theoretically scalable to 881 physical qubits (supporting a distance-21 surface code) while maintaining sub-microsecond latency, thereby demonstrating, for the first time, a complete low-latency closed-loop QEC pipeline spanning control, communication, and decoding.

Technology Category

• Machine Learning: Quantum Machine Learning
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Economics, Online Markets and Human Computation: LLM based quality controls for crowd work
• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Search and Retrieval-Augmented AI: Retrieval-Augmented Generation (RAG) and multi-modal RAG

Abstract

Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.

Problem

• Quantum Error Correction
• Low-Latency Decoding
• Real-Time Control
• Scalable Architecture
• Fault-Tolerant Quantum Computation

Innovation

• quantum error correction
• sub-microsecond latency
• RISC-V quantum control
• RFSoC FPGA
• scalable QEC architecture