🤖 AI Summary
DRAM maintenance operations—such as refresh, RowHammer mitigation, and scrubbing—have traditionally required tight coordination with the memory controller, necessitating modifications to DRAM interfaces and standards, thereby impeding adoption of novel architectures. This paper proposes Self-Managing DRAM (SMD), the first design to fully decentralize maintenance control onto the DRAM die, enabling autonomous, parallel, and low-overhead in-DRAM management via minimal interface extensions (e.g., bank-level access rejection signals). Key contributions include: (1) a DDRx-compatible microarchitecture requiring zero additional pins; (2) cross-bank overlap of maintenance and memory accesses; and (3) forward progress guarantees for rejected requests. Evaluated on 20 memory-intensive four-core workloads, SMD achieves an average 4.1% performance improvement over DDR4-based cooperative optimization baselines, with negligible area and latency overhead. All code and evaluation data are publicly released.
📝 Abstract
The memory controller is in charge of managing DRAM maintenance operations (e.g., refresh, RowHammer protection, memory scrubbing) to reliably operate modern DRAM chips. Implementing new maintenance operations often necessitates modifications in the DRAM interface, memory controller, and potentially other system components. Such modifications are only possible with a new DRAM standard, which takes a long time to develop, likely leading to slow progress in the adoption of new architectural techniques in DRAM chips. We propose a new low-cost DRAM architecture, Self-Managing DRAM (SMD), that enables autonomous in-DRAM maintenance operations by transferring the responsibility for controlling maintenance operations from the memory controller to the SMD chip. To enable autonomous maintenance operations, we make a single modification to the DRAM interface, such that an SMD chip rejects memory controller accesses to DRAM regions under maintenance, while allowing memory accesses to others. Thus, SMD enables 1) implementing new in-DRAM maintenance mechanisms (or modifying existing ones) with no further changes in the DRAM interface or other system components, and 2) overlapping the latency of a maintenance operation in one DRAM region with the latency of accessing data in another. We evaluate SMD and show that it 1) can be implemented without adding new pins to the DDRx interface with low latency and area overhead, 2) achieves 4.1% average speedup across 20 four-core memory-intensive workloads over a DDR4-based system/DRAM co-design technique that intelligently parallelizes maintenance operations with memory accesses, and 3) guarantees forward progress for rejected memory accesses. We believe and hope SMD can enable innovations in DRAM architecture to rapidly come to fruition. We open source all SMD source code and data at https://github.com/CMU-SAFARI/SelfManagingDRAM.
