TSPC-PFD: TSPC-Based Low-Power High-Resolution CMOS Phase Frequency Detector

2025-08-23

AI Summary

Conventional phase-frequency detectors (PFDs) suffer from significant blind and dead zones at high frequencies, leading to increased phase detection error and output jitter. To address this, this work proposes a low-power, high-precision CMOS PFD based on true single-phase clocking (TSPC), which completely eliminates the blind zone and reduces the dead zone to 40 ps. Implemented in TSMC 28 nm CMOS technology, the proposed PFD consumes only 4.41 μW at a 3 GHz input frequency and occupies a compact core area of 10.42 μm². Compared with state-of-the-art designs, it achieves superior phase detection accuracy and energy efficiency while maintaining high-speed response. The design is particularly well-suited for high-performance phase-locked loops (PLLs) and delay-locked loops (DLLs), where stringent timing precision and low power consumption are critical.

Technology Category

Machine Learning: Hardware-aware MLConstraint Satisfaction and Optimization: Distributed CSP/OptimizationComputer Vision: Low Level & Physics-based Vision

Application Category

Security and Privacy: Large-scale security measurementsSystems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environmentsUser Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation

Abstract

Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps and/or, consequently, Voltage-Controlled Oscillators (VCOs). Conventional PFD designs often suffer from significant dead zones and blind zones, which degrade phase detection accuracy and increase jitter in high-speed applications. This paper addresses PFD design challenges and presents a novel low-power True Single-Phase Clock (TSPC)-based PFD. The proposed design eliminates the blind zone entirely while achieving a minimal dead zone of 40 ps. The proposed PFD, implemented using TSMC 28 nm technology, demonstrates a low-power consumption of 4.41 uW at 3 GHz input frequency with a layout area of $10.42μm^2$.

Problem

• Eliminates blind zone in phase frequency detectors
• Minimizes dead zone to 40 ps for accuracy
• Reduces power consumption in high-speed PLL systems

Innovation

• TSPC-based phase frequency detector design
• Eliminates blind zone with minimal dead zone
• Low-power 28nm CMOS implementation