VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration

2025-06-04

AI Summary

To address the inefficiency and heavy reliance on manual effort in classifying erroneous waveforms and localizing faults during RTL-level simulation failures, this paper proposes an automated root-cause localization method based on Value Change Dump (VCD) waveforms. We innovatively design a signal selection and statistical compression strategy that preserves discriminative temporal features while achieving over 120× waveform data reduction. A lightweight machine learning classifier is then built to enable cross-design and cross-platform deployment. Evaluated on large-scale industrial RTL designs, the method achieves 94.2% accuracy in ranking the top three suspicious modules. It is the first approach to deliver high-accuracy, transferable, and low-overhead automatic attribution of RTL simulation failures, significantly reducing manual waveform analysis time. This work provides a key enabling technology for closing the functional verification loop.

Technology Category

• Machine Learning: Calibration & Uncertainty Quantification
• Knowledge Representation and Reasoning: Diagnosis and Abductive Reasoning
• Data Mining & Knowledge Management: Anomaly/Outlier Detection

Application Category

• Responsible Web: Machine-in-the-loop, human agency and autonomy
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Web Mining and Content Analysis: Robustness and generalizability of Web mining methods

Abstract

Failure triage in design functional verification is critical but time-intensive, relying on manual specification reviews, log inspections, and waveform analyses. While machine learning (ML) has improved areas like stimulus generation and coverage closure, its application to RTL-level simulation failure triage, particularly for large designs, remains limited. VCDiag offers an efficient, adaptable approach using VCD data to classify failing waveforms and pinpoint likely failure locations. In the largest experiment, VCDiag achieves over 94% accuracy in identifying the top three most likely modules. The framework introduces a novel signal selection and statistical compression approach, achieving over 120x reduction in raw data size while preserving features essential for classification. It can also be integrated into diverse Verilog/SystemVerilog designs and testbenches.

Problem

• Classifying erroneous waveforms to accelerate failure triage
• Reducing manual effort in RTL-level simulation failure analysis
• Compressing VCD data while preserving classification features

Innovation

• Uses VCD data for waveform classification
• Introduces signal selection and compression
• Achieves 120x data reduction