Transaction Level Hierarchy Guided and Functional Coverage Driven Deductive Formal Verification

๐Ÿ“… 2025-01-02
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๐Ÿค– AI Summary
In hardware logic verification, conventional dynamic simulation and module-level approaches fail to ensure comprehensive transaction-level functional coverage and suffer from poor verification result reusability. This paper proposes the first transaction-level (TL) hierarchical deductive formal verification framework. It extends the PDVL language to support functional coverage and assertion modeling, compiles PDVL specifications into Coq-verifiable Gallina code, and automates the translation of functional coverage goals into proof obligations. The framework enables cross-layer verification reuse and supports formal verification of SVA assertions. Crucially, achieving 100% functional coverage is formally equivalent to establishing system completenessโ€”a rigorous proof of correctness. Our approach delivers high verification accuracy while significantly improving reusability and efficiency over traditional assertion-based verification (ABV) and simulation hybrid methods.

Technology Category

Knowledge Representation and Reasoning: Description LogicsMachine Learning: Hardware-aware MLConstraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applicationsEconomics, Online Markets and Human Computation: Cost models of using LLMs in production systemsSemantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions
๐Ÿ“ Abstract
We demonstrate how dynamic verification (e.g. simulation) can be replaced by deductive formal verification and how to benefit from the advantages of symbolic verification and the reuse of verification proofs. To do this, we swap the well-known module-hierarchy based concept with a transaction-level (TL) based alternative, which still allows us to describe the design as precisely as on RTL. We enhance the aspect-oriented and TL oriented language PDVL to support the definition of functional coverage (FC) and assertions at all levels of a TL-hierarchy. We then show how to use a deductive formal verification (DFV) flow which compiles PDVL code into Gallina code to be used by the Coq theorem prover. It can be argued that FC can be converted into proof obligations and that proving them is equivalent to 100% coverage. We also demonstrate how lower-level proofs can be reused when verifying aspects at higher-levels of a TL-hierarchy. We argue that the traditional assertion-based verification (ABV) methodology is still supported and SVA can be proven using DFV.
Problem

Research questions and friction points this paper is trying to address.

Hardware Design Verification
Transactional Level
Functional Coverage
Innovation

Methods, ideas, or system contributions that make the work stand out.

Symbolic Verification
PDVL to Gallina Translation
Hierarchical Design Validation
EDAptix e.K.
T
Tobias Strauch
R&D, EDAptix e.K., Munich, Germany