FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm

2025-06-09

AI Summary

Dynamic out-of-order execution remains challenging to teach and intuitively grasp in computer architecture courses. Method: This paper designs and implements an open-source, interactive, RISC-V–style superscalar processor educational simulator based on an extended Tomasulo algorithm. It comprehensively models key pipeline stages—instruction fetch, register renaming, issue, execution, and commit—and introduces a novel, pedagogy-oriented, configurable microarchitectural framework supporting parameterized functional units, instruction window, reorder buffer (ROB), and register alias table. Contribution/Results: The simulator enables full-pipeline visualization, custom instruction program execution, adjustable architectural parameters, and three canonical illustrative case studies to concretely demonstrate multi-instruction parallelism per cycle. Experimental evaluation confirms that the tool significantly enhances students’ conceptual understanding of instruction-level parallelism, dynamic scheduling, and out-of-order execution mechanisms.

Technology Category

• Cognitive Modeling & Cognitive Systems: Simulating Human Behavior
• Planning, Routing, and Scheduling: Model-Based Reasoning
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• User Modeling, Personalization and Recommendation: User modeling and simulation for interactive and conversational systems
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking

Abstract

FREESS is a free, interactive simulator that illustrates instruction-level parallelism in a RISC-V-inspired superscalar processor. Based on an extended version of Tomasulo's algorithm, FREESS is intended as a hands-on educational tool for Advanced Computer Architecture courses. It enables students to explore dynamic, out-of-order instruction execution, emphasizing how instructions are issued as soon as their operands become available. The simulator models key microarchitectural components, including the Instruction Window (IW), Reorder Buffer (ROB), Register Map (RM), Free Pool (FP), and Load/Store Queues. FREESS allows users to dynamically configure runtime parameters, such as the superscalar issue width, functional unit types and latencies, and the sizes of architectural buffers and queues. To simplify learning, the simulator uses a minimal instruction set inspired by RISC-V (ADD, ADDI, BEQ, BNE, LW, MUL, SW), which is sufficient to demonstrate key pipeline stages: fetch, register renaming, out-of-order dispatch, execution, completion, commit, speculative branching, and memory access. FREESS includes three step-by-step, illustrated examples that visually demonstrate how multiple instructions can be issued and executed in parallel within a single cycle. Being open source, FREESS encourages students and educators to experiment freely by writing and analyzing their own instruction-level programs and superscalar architectures.

Problem

• Simulates RISC-V superscalar processor with Tomasulo's algorithm
• Teaches dynamic out-of-order instruction execution concepts
• Configurable parameters for hands-on computer architecture education

Innovation

• RISC-V-inspired superscalar processor simulator
• Extended Tomasulo's algorithm for education
• Dynamic configuration of runtime parameters