FPGA-Based Multiplier with a New Approximate Full Adder for Error-Resilient Applications

2025-06-11

AI Summary

To address the trade-off among high power consumption, low speed, and limited accuracy in VLSI signal processing multipliers, this paper proposes an FPGA-based multiplier architecture built upon a novel approximate full adder. The design enables parallel accumulation of adjacent-bit partial products, significantly shortening the critical path, and employs approximation computing to reduce hardware overhead, with end-to-end validation in a mean filtering system. Experimental results demonstrate a 56.09% reduction in multiplier power consumption and a 73.02% improvement in power-delay product. At the system level, power consumption is reduced by 33.33%, while image fidelity metrics improve substantially—PSNR increases by 30.58% and SSIM by 22.22%—outperforming state-of-the-art approximate multipliers. This work achieves a superior balance among low power, high throughput, and high fidelity.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Multi-modal Vision
• Search and Optimization: Learning to Search

Application Category

• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Retrieval-Augmented Generation (RAG) and multi-modal RAG
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Electronic devices primarily aim to offer low power consumption, high speed, and a compact area. The performance of very large-scale integration (VLSI) devices is influenced by arithmetic operations, where multiplication is a crucial operation. Therefore, a high-speed multiplier is essential for developing any signal-processing module. Numerous multipliers have been reviewed in existing literature, and their speed is largely determined by how partial products (PPs) are accumulated. To enhance the speed of multiplication beyond current methods, an approximate adder-based multiplier is introduced. This approach allows for the simultaneous addition of PPs from two consecutive bits using a novel approximate adder. The proposed multiplier is utilized in a mean filter structure and implemented in ISE Design Suite 14.7 using VHDL and synthesized on the Xilinx Spartan3-XC3S400 FPGA board. Compared to the literature, the proposed multiplier achieves power and power-delay product (PDP) improvements of 56.09% and 73.02%, respectively. The validity of the expressed multiplier is demonstrated through the mean filter system. Results show that it achieves power savings of 33.33%. Additionally, the proposed multiplier provides more accurate results than other approximate multipliers by expressing higher values of peak signal-to-noise ratio (PSNR), (30.58%), and structural similarity index metric (SSIM), (22.22%), while power consumption is in a low range.

Problem

• Design low-power high-speed FPGA-based multiplier
• Improve multiplication speed using approximate adder
• Enhance accuracy in error-resilient signal processing

Innovation

• FPGA-based multiplier with approximate adder
• Simultaneous addition of partial products
• Improved power efficiency and accuracy