Problem
Research questions and friction points this paper is trying to address.
Backside Clock Mesh
Design Space Exploration
BSPDN
GAAFET
Clock Skew
Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology
🤖 AI Summary
This study addresses the excessive front-side routing resource consumption and high skew associated with high-performance VLSI clock meshes by presenting the first exploration of backside clock mesh design spaces in 2nm backside power delivery (BSPDN) technologies. The proposed methodology leverages thick backside metal layers to optimize clock distribution, connecting to front-end flip-flops through-silicon vias (TSVs). Design and verification are conducted on the OpenROAD platform using the GT2N process technology, integrating multi-objective Bayesian optimization, transistor-level SPICE simulations, and Monte Carlo analysis. Experimental results demonstrate that, compared to conventional front-side clock meshes, the proposed approach reduces skew, slew rate, power consumption, and front-side routing congestion by an average of 45%, 25%, 4.5%, and 28%, respectively, while significantly enhancing resilience against process variations.
📝 Abstract
Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power delivery creates a new option: it adds thick, low-resistance metal layers on the back of the wafer, and the power grid does not consume all of them. Flip-flops remain on the frontside; a backside mesh therefore cannot drive them directly, and every connection passes through a through-silicon via. We present the first design-space exploration of backside clock meshes, implemented in OpenROAD on GT2N, a 2 nm nanosheet technology. Four benchmarks (1,938 to 15,311 flip-flops) are explored with multi-objective Bayesian optimization, and every design point is verified by transistor-level SPICE simulation, since the cyclic mesh cannot be evaluated by static timing analysis. Across all four designs, the backside mesh consistently outperforms an identical frontside mesh, with on average 45% lower skew, 25% lower sink slew, 4.5% lower power, and 28% less frontside clock wiring, and its skew spread under 10,000-sample Monte Carlo is a third of the frontside mesh's.
Innovation
Methods, ideas, or system contributions that make the work stand out.
Backside Clock Mesh
Design Space Exploration
Bayesian Optimization
BSPDN
GAAFET
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