Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security

2026-02-04

AI Summary

This work addresses the lack of efficient hardware support for both conventional and post-quantum cryptographic algorithms on existing RISC-V platforms, which hinders their deployment in resource-constrained environments such as IoT. To this end, the authors design and implement a high-energy-efficiency FPGA-based cryptographic coprocessor tailored for the RISC-V architecture, providing unified acceleration for SHA, SM3, AES, and HARAKA. The design innovatively integrates a high-bandwidth internal buffer, dedicated cryptographic execution units, a four-stage pipeline, and a dual-buffer adaptive scheduling mechanism optimized for large hash computations. Implemented on a Xilinx ZCU102 platform, the coprocessor operates at 160 MHz with a power consumption of only 0.851 W, achieving 165–1061× speedup over a baseline RISC-V core and surpassing high-performance CPUs in energy efficiency by 5.8–17.4×, while occupying merely 34,704 LUTs.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Adversarial Attacks & Robustness
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures

Application Category

• Security and Privacy: Applications of cryptography
• Search and Retrieval-Augmented AI: Retrieval-Augmented Generation (RAG) and multi-modal RAG
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments

Abstract

Cryptographic operations are critical for securing IoT, edge computing, and autonomous systems. However, current RISC-V platforms lack efficient hardware support for comprehensive cryptographic algorithm families and post-quantum cryptography. This paper presents Crypto-RV, a RISC-V co-processor architecture that unifies support for SHA-256, SHA-512, SM3, SHA3-256, SHAKE-128, SHAKE-256 AES-128, HARAKA-256, and HARAKA-512 within a single 64-bit datapath. Crypto-RV introduces three key architectural innovations: a high-bandwidth internal buffer (128x64-bit), cryptography-specialized execution units with four-stage pipelined datapaths, and a double-buffering mechanism with adaptive scheduling optimized for large-hash. Implemented on Xilinx ZCU102 FPGA at 160 MHz with 0.851 W dynamic power, Crypto-RV achieves 165 times to 1,061 times speedup over baseline RISC-V cores, 5.8 times to 17.4 times better energy efficiency compared to powerful CPUs. The design occupies only 34,704 LUTs, 37,329 FFs, and 22 BRAMs demonstrating viability for high-performance, energy-efficient cryptographic processing in resource-constrained IoT environments.

Problem

• RISC-V
• cryptographic co-processor
• IoT security
• post-quantum cryptography
• hardware acceleration

Innovation

• RISC-V co-processor
• post-quantum cryptography
• hardware acceleration
• energy-efficient FPGA
• unified cryptographic datapath