EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques

2025-06-12

AI Summary

Existing FPGA-based evaluation platforms for emerging DRAM technologies face two key bottlenecks: high HDL development overhead and inaccurate modeling of modern processor–DRAM frequency mismatches. This paper introduces the first open-source FPGA evaluation infrastructure tailored for emerging DRAMs. Our approach centers on (1) a C++-based programmable memory controller that eliminates HDL dependency, and (2) a time-scaling mechanism enabling precise cross-frequency-domain timing modeling. The framework supports end-to-end, quantitative evaluation—on real DRAM chips—of how new DRAM technologies impact system throughput, reliability, and compute-in-memory capabilities. Experimental results demonstrate substantial improvements in both evaluation efficiency and timing fidelity. The infrastructure is fully open-sourced, providing a reproducible, extensible co-verification platform for memory-system innovation.

Technology Category

• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems
• Cognitive Modeling & Cognitive Systems: Other Foundations of Cognitive Modeling & Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Economics, Online Markets and Human Computation: Economic ramifications for generative AI infrastructure and applications

Abstract

DRAM is a critical component of modern computing systems. Recent works propose numerous techniques (that we call DRAM techniques) to enhance DRAM-based computing systems' throughput, reliability, and computing capabilities (e.g., in-DRAM bulk data copy). Evaluating the system-wide benefits of DRAM techniques is challenging as they often require modifications across multiple layers of the computing stack. Prior works propose FPGA-based platforms for rapid end-to-end evaluation of DRAM techniques on real DRAM chips. Unfortunately, existing platforms fall short in two major aspects: (1) they require deep expertise in hardware description languages, limiting accessibility; and (2) they are not designed to accurately model modern computing systems. We introduce EasyDRAM, an FPGA-based framework for rapid and accurate end-to-end evaluation of DRAM techniques on real DRAM chips. EasyDRAM overcomes the main drawbacks of prior FPGA-based platforms with two key ideas. First, EasyDRAM removes the need for hardware description language expertise by enabling developers to implement DRAM techniques using a high-level language (C++). At runtime, EasyDRAM executes the software-defined memory system design in a programmable memory controller. Second, EasyDRAM tackles a fundamental challenge in accurately modeling modern systems: real processors typically operate at higher clock frequencies than DRAM, a disparity that is difficult to replicate on FPGA platforms. EasyDRAM addresses this challenge by decoupling the processor-DRAM interface and advancing the system state using a novel technique we call time scaling, which faithfully captures the timing behavior of the modeled system. We believe and hope that EasyDRAM will enable innovative ideas in memory system design to rapidly come to fruition. To aid future research EasyDRAM implementation is open sourced at https://github.com/CMU-SAFARI/EasyDRAM.

Problem

• Enables rapid evaluation of DRAM techniques on real chips
• Simplifies implementation using high-level language (C++)
• Accurately models modern processor-DRAM frequency disparities

Innovation

• FPGA-based framework for DRAM evaluation
• High-level C++ programming for memory design
• Time scaling for accurate system modeling