PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips

2025-06-15

AI Summary

This work identifies PuDHammer, a novel read-disturb attack in Processing-using-DRAM (PuD) architectures, triggered by multi-row activation—distinct from conventional single-row RowHammer. PuDHammer exacerbates DRAM read disturbance, reducing the number of hammering operations required to induce first-bit flips by up to 158.58× and evading target-row refresh defenses while synergistically amplifying errors with RowHammer. Method: We conduct hardware fault injection and large-scale characterization across 316 real-world DDR4 chips from multiple vendors and process nodes to quantify cross-manufacturer and cross-process sensitivity variations. Contribution/Results: We provide the first systematic empirical foundation for reliability assessment and security design of PuD systems. We propose three hardware–software co-design mitigation strategies; among them, adaptation of the PRAC mechanism incurs an average performance overhead of 48.26%. Our findings expose critical vulnerability vectors in emerging in-memory computing paradigms and establish benchmarks for future secure PuD architecture development.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Distributed Search
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems

Application Category

• Security and Privacy: Large-scale security measurements
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

Processing-using-DRAM (PuD) is a promising paradigm for alleviating the data movement bottleneck using DRAM's massive internal parallelism and bandwidth to execute very wide operations. Performing a PuD operation involves activating multiple DRAM rows in quick succession or simultaneously, i.e., multiple-row activation. Multiple-row activation is fundamentally different from conventional memory access patterns that activate one DRAM row at a time. However, repeatedly activating even one DRAM row (e.g., RowHammer) can induce bitflips in unaccessed DRAM rows because modern DRAM is subject to read disturbance. Unfortunately, no prior work investigates the effects of multiple-row activation on DRAM read disturbance. In this paper, we present the first characterization study of read disturbance effects of multiple-row activation-based PuD (which we call PuDHammer) using 316 real DDR4 DRAM chips from four major DRAM manufacturers. Our detailed characterization show that 1) PuDHammer significantly exacerbates the read disturbance vulnerability, causing up to 158.58x reduction in the minimum hammer count required to induce the first bitflip ($HC_{first}$), compared to RowHammer, 2) PuDHammer is affected by various operational conditions and parameters, 3) combining RowHammer with PuDHammer is more effective than using RowHammer alone to induce read disturbance error, e.g., doing so reduces $HC_{first}$ by 1.66x on average, and 4) PuDHammer bypasses an in-DRAM RowHammer mitigation mechanism (Target Row Refresh) and induces more bitflips than RowHammer. To develop future robust PuD-enabled systems in the presence of PuDHammer, we 1) develop three countermeasures and 2) adapt and evaluate the state-of-the-art RowHammer mitigation standardized by industry, called Per Row Activation Counting (PRAC). We show that the adapted PRAC incurs large performance overheads (48.26%, on average).

Problem

• Investigates read disturbance effects of multiple-row activation in DRAM
• Analyzes PuDHammer's impact on DRAM vulnerability and bitflip rates
• Evaluates countermeasures for robust Processing-using-DRAM systems

Innovation

• Multiple-row activation in DRAM for processing
• Characterization of PuDHammer read disturbance effects
• Countermeasures and PRAC adaptation for robustness