Cut Tracing with E-Graphs for Boolean FHE Circuit Synthesis

2025-06-15

AI Summary

The high runtime overhead of fully homomorphic encryption (FHE) circuits stems from the coupled growth of multiplicative depth (MD) and multiplicative complexity (MC): optimizing either metric in isolation often degrades the other, and existing approaches lack joint optimization targeting overall runtime. Method: This work introduces e-graphs—the first application of this formalism to FHE circuit optimization—and proposes cut tracing, a novel technique that jointly minimizes MD and MC at the logic synthesis level. By integrating Boolean circuit optimization, cut enumeration, and a multi-objective optimization framework, our method achieves end-to-end integration within two state-of-the-art optimization flows. Contribution/Results: Our approach reduces homomorphic evaluation runtime by up to 40% compared to baseline methods, significantly outperforming single-objective optimization strategies while preserving correctness and security guarantees.

Technology Category

• Search and Optimization: Heuristic Search
• Machine Learning: Optimization
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Security and Privacy: Applications of cryptography
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

Fully Homomorphic Encryption (FHE) is a promising privacy-preserving technology enabling secure computation over encrypted data. A major limitation of current FHE schemes is their high runtime overhead. As a result, automatic optimization of circuits describing FHE computation has garnered significant attention in the logic synthesis community. Existing works primarily target the multiplicative depth (MD) and multiplicative complexity (MC) of FHE circuits, corresponding to the total number of multiplications and maximum number of multiplications in a path from primary input to output, respectively. In many FHE schemes, these metrics are the primary contributors to the homomorphic evaluation runtime of a circuit. However, oftentimes they are opposed: reducing either depth or complexity may result in an increase in the other. To our knowledge, existing works have yet to optimize FHE circuits for overall runtime, only considering one metric at a time and thus making significant tradeoffs. In this paper, we use e-graphs to augment existing flows that individually optimize MC and MD, in a technique called cut tracing. We show how cut tracing can effectively combine two state-of-the-art MC and MD reduction flows and balance their weaknesses to minimize runtime. Our preliminary results demonstrate that cut tracing yields up to a 40% improvement in homomorphic evaluation runtime when applied to these two flows.

Problem

• Optimize FHE circuits for overall runtime
• Balance multiplicative depth and complexity tradeoffs
• Improve homomorphic evaluation runtime by 40%

Innovation

• Uses e-graphs for FHE circuit optimization
• Combines MC and MD reduction flows
• Improves runtime by up to 40%