Application of Machine Learning for Correcting Defect-induced Neuromorphic Circuit Inference Errors

2025-09-14

AI Summary

To address the significant degradation in inference accuracy caused by spatially fixed defects—such as ring-, row-, column-, and checkerboard-patterned faults—in ReRAM-based analog neuromorphic circuits, this work proposes a lightweight neural network-based output voltage correction method. Unlike conventional approaches, it requires no prior knowledge of defect types; instead, it learns a correction mapping solely from the circuit’s raw output voltages, enabling generalization to unseen defect configurations. The method is inherently extensible to dynamic degradation and aging-related faults, supporting real-time adaptive learning. Evaluated within a Design-Technology Co-Optimization (DTCO) simulation framework on the MNIST handwritten digit recognition task, the correction network restores inference accuracy from 55% to 90% under defect conditions—a 35-percentage-point improvement. This work establishes a low-overhead, scalable, and highly robust fault-tolerance paradigm for neuromorphic chips targeting edge and IoT applications.

Technology Category

Machine Learning: Hardware-aware MLComputer Vision: Adversarial Attacks & RobustnessCognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for rankingEconomics, Online Markets and Human Computation: Data quality aspects of human-annotated datasetsGraph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs

Abstract

This paper presents a machine learning-based approach to correct inference errors caused by stuck-at faults in fully analog ReRAM-based neuromorphic circuits. Using a Design-Technology Co-Optimization (DTCO) simulation framework, we model and analyze six spatial defect types-circular, circular-complement, ring, row, column, and checkerboard-across multiple layers of a multi-array neuromorphic architecture. We demonstrate that the proposed correction method, which employs a lightweight neural network trained on the circuit's output voltages, can recover up to 35% (from 55% to 90%) inference accuracy loss in defective scenarios. Our results, based on handwritten digit recognition tasks, show that even small corrective networks can significantly improve circuit robustness. This method offers a scalable and energy-efficient path toward enhanced yield and reliability for neuromorphic systems in edge and internet-of-things (IoTs) applications. In addition to correcting the specific defect types used during training, our method also demonstrates the ability to generalize-achieving reasonable accuracy when tested on different types of defects not seen during training. The framework can be readily extended to support real-time adaptive learning, enabling on-chip correction for dynamic or aging-induced fault profiles.

Problem

• Correcting inference errors from defects in analog neuromorphic circuits
• Modeling spatial defect types in multi-layer ReRAM arrays
• Recovering accuracy loss with lightweight neural network correction

Innovation

• Machine learning corrects neuromorphic circuit defects
• Lightweight neural network recovers inference accuracy loss
• Scalable method enhances yield for edge IoT systems