IMITATOR4AMAS: Strategy Synthesis for STCTL

2026-02-11

AI Summary

This work addresses the lack of efficient memoryless strategy synthesis methods for STCTL logic under imperfect information in networks of parametric timed automata. Building upon the extended verification tool IMITATOR, it presents the first implementation of STCTL model checking and memoryless strategy synthesis under asynchronous execution semantics. By integrating parametric timed automata, STCTL semantics, and an algorithm for strategy synthesis under imperfect information, the proposed approach overcomes existing limitations in both expressiveness and computational efficiency. Experimental results demonstrate a significant improvement in strategy synthesis speed compared to prior methods.

Technology Category

Game Theory and Economic Paradigms: Imperfect InformationConstraint Satisfaction and Optimization: Satisfiability Modulo TheoriesMultiagent Systems: Mechanism Design

Application Category

Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMsEconomics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystemsGraph Algorithms and Modeling for the Web: Algorithms and analysis for incomplete, noisy, or partially observed Web-related graphs

Abstract

IMITATOR4AMAS supports model checking and synthesis of memoryless imperfect information strategies for STCTL, interpreted over networks of parametric timed automata with asynchronous execution. While extending the verifier IMITATOR, IMITATOR4AMAS is the first tool for strategy synthesis in this setting. Our experimental results show a substantial speedup over previous approaches.

Problem

• strategy synthesis
• imperfect information
• parametric timed automata
• STCTL
• asynchronous execution

Innovation

• strategy synthesis
• parametric timed automata
• imperfect information
• STCTL
• asynchronous execution