Power- and Area-Efficient Unary Sorting Architecture Using FSM-Based Unary Number Generator

2025-06-27

AI Summary

Conventional unary computing hardware sorters suffer from excessive area and power overhead due to complex unary number generators. Method: This work proposes a right-aligned unary stream generation mechanism based on a two-state finite-state machine (FSM), enabling comparison-free, iterative ascending sorting. By eliminating conventional comparators, the FSM efficiently generates unary codes and dynamically identifies the minimum value, drastically simplifying hardware architecture. Contribution/Results: Synthesis results in 45 nm CMOS technology demonstrate an 82% reduction in area and a 70% reduction in power consumption compared to state-of-the-art unary sorters. To our knowledge, this is the first work to employ a lightweight FSM for unary number generation—achieving both high energy efficiency and low hardware overhead. The approach establishes a scalable, resource-efficient hardware sorting paradigm tailored for edge devices with stringent constraints on area, power, and latency.

Technology Category

• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Data Stream Mining
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• User Modeling, Personalization and Recommendation: Fairness-aware retrieval and ranking

Abstract

Sorting is a fundamental operation in computer systems and is widely used in applications such as databases, data analytics, and hardware accelerators. Unary computing has recently emerged as a low-cost and power-efficient paradigm for implementing hardware sorters by eliminating the need for complex arithmetic operations. However, existing comparison-free unary computing-based designs suffer from significant area and power overhead due to costly unary number generators. In this paper, we present a novel ascending-order unary sorting module featuring a finite-state-machine-based unary number generator that significantly reduces implementation costs. By generating right-aligned unary streams using a two-state finite-state machine, our architecture iteratively identifies the minimum input value in each cycle without conventional comparators. Synthesis results in a 45nm technology node demonstrate up to 82% reduction in area and 70% reduction in power consumption compared to state-of-the-art unary designs. The proposed sorter offers a promising solution for energy-constrained and resource-limited hardware systems.

Problem

• Reducing area and power in unary sorting architectures
• Eliminating costly unary number generators in hardware sorters
• Improving efficiency for energy-constrained hardware systems

Innovation

• FSM-based unary number generator
• Right-aligned unary streams
• Two-state finite-state machine