Fast Iterative Dual-Output-Aware LUT Mapping for Fracturable FPGA Architectures

2026-07-23

AI Summary

This work addresses the limitation of traditional FPGA mapping, which performs dual-output packing only after single-output LUT mapping, thereby overlooking pairing optimization opportunities during cut selection. The authors propose an iterative, dual-output-aware LUT mapping framework that, for the first time, feeds dual-output pairing information forward into the cut selection phase and integrates it into Berkeley ABC. The method alternates between cut selection and constrained dual-output matching by generating candidate pairs via sparse support indexing, scoring matches heuristically, adjusting cut costs with compatibility awareness, and validating architectural legality and timing based on physical input unions. Evaluated on EPFL benchmarks, the approach reduces LUT area by 34.96% on average compared to the original ABC, achieves a 15.8× speedup over the previous best method, and further lowers circuit depth by approximately 5% while reducing area by an additional 1%.

Abstract

Modern field-programmable gate arrays employ fracturable lookup tables (LUTs), each of which can implement either a single large-input function or two smaller functions within a shared physical LUT site. Conventional technology-mapping flows typically perform dual-output packing only after single-output LUT mapping, thereby preventing potential pairing opportunities from influencing cut selection. This paper presents an iterative dual-output-aware LUT-mapping framework integrated into the delay, area-flow, and exact-area optimization passes of the Berkeley ABC mapper. The proposed method alternates between single-output cut selection and bounded dual-output matching. Candidate pairs are efficiently generated using a sparse support-based index, validated against parameterized architectural, dependency, and output-specific timing constraints, and selected through a heuristic score-based matching procedure. The resulting partner information is then fed back into subsequent mapping rounds through a compatibility-aware cut-cost adjustment. To preserve timing accuracy, the physical union of the inputs is used only for architectural legality checking, while each output retains its own logical timing support. Experiments on the EPFL combinational benchmark suite under two representative architecture models demonstrate average reductions of 34.96% and 23.39% in the reported LUT-area metric relative to vanilla ABC. Compared with the best previously reported method, the proposed framework achieves a 15.8 times speedup while further reducing depth by approximately 5% and area by 1%.

Problem

• fracturable LUT
• dual-output packing
• technology mapping
• FPGA architecture
• cut selection

Innovation

• dual-output-aware mapping
• fracturable LUT
• iterative LUT mapping
• sparse support indexing
• compatibility-aware cost adjustment