The Sparsity Tax: Weight Sparsity Trade-offs in Event-Driven SIMD and SIMT Neuromorphic Cores

2026-07-24

AI Summary

This work addresses the irregular memory access induced by weight sparsity in event-driven SIMD/SIMT neuromorphic computing, which incurs a “sparsity tax” manifested in increased control complexity, metadata overhead, and reduced memory efficiency. For the first time, this study quantifies this sparsity tax and proposes three closely related accelerator architectures: a baseline SIMD, a bitmap-gated Sparse-SIMD, and an SIMT design leveraging run-length encoded (RLE) sparse weights. Evaluated via RTL-to-gate implementation in GF22FDX+ technology combined with an activity-driven energy model, results show that SRAM-dominated area limits total area variation; SIMT achieves substantial gains in energy efficiency and performance at high sparsity levels, albeit constrained by metadata bandwidth and workload imbalance; Sparse-SIMD yields only modest improvements due to bitmap and dense-storage overheads.

Abstract

Event-driven neuromorphic inference exploits activation sparsity by updating neuron state only on spikes. However, weight sparsity introduces irregular gather-style updates that undermine lockstep Single Instruction Multiple Data (SIMD) execution. We call the resulting overheads in control, metadata, and memory activity the sparsity tax. This paper quantifies that tax by comparing three closely related accelerators integrated into one neuromorphic core: (i) baseline lockstep SIMD, (ii) bitmap-gated Sparse-SIMD that selectively disables lanes without compressing weights, and (iii) a Single Instruction Multiple Threads (SIMT) style design with per-PE address generation and run-length coded sparse weights. Using an RTL-to-gates flow in GF22FDX+ and activity-driven energy estimation, we evaluate event-driven neural network inference across varying post-training pruning levels. Results show that total core area changes are insignificant because SRAM dominates area, while performance and energy strongly depend on how sparsity is handled: SIMD and Sparse-SIMD exhibit near-constant throughput, Sparse-SIMD achieves limited energy savings due to bitmap and dense-storage overheads, and SIMT provides the strongest energy scaling and substantial speedups at high sparsity, albeit with sublinear gains due to metadata reads, load imbalance, and sparsity-independent phases. The hardware code for the proposed architectures and experiments is publicly accessible for research purposes.

Problem

• sparsity tax
• weight sparsity
• event-driven neuromorphic
• SIMD
• SIMT

Innovation

• sparsity tax
• event-driven neuromorphic computing
• SIMT architecture
• weight sparsity
• Sparse-SIMD